Coded data generation or conversion – Converter compensation
Reexamination Certificate
2007-01-09
2007-01-09
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Converter compensation
C341S172000
Reexamination Certificate
active
11217154
ABSTRACT:
An error correction circuit for use with an analog-to-digital converter (ADC) comprising correction capacitance switching means coupled to the correction capacitance means. The switching means being coupled to ground and to a plurality of reference voltages and being arranged to a couple a bottom plate of the correction capacitance means to ground during a sample phase of the ADC and to one of a plurality of reference voltages during a hold phase of the ADC.
REFERENCES:
patent: 5012247 (1991-04-01), Dillman
patent: 5134401 (1992-07-01), McCartney et al.
patent: 5852415 (1998-12-01), Cotter et al.
patent: 6304208 (2001-10-01), Nagashima
patent: 6433712 (2002-08-01), Ohnhaeuser et al.
patent: 6720903 (2004-04-01), Confalonieri et al.
patent: 6870496 (2005-03-01), Krymski et al.
patent: 2003/0063026 (2003-04-01), Nandy
patent: 2005/0123072 (2005-06-01), Guimaraes
Brown Charles D.
Loomis Timothy F.
Qualcomm Inc.
Wadsworth Philip R.
Williams Howard L.
LandOfFree
Gain error correction in an analog-to-digital converter does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Gain error correction in an analog-to-digital converter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gain error correction in an analog-to-digital converter will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3746159