Gain control circuitry for delay locked loop circuit

Details Gain control circuitry for delay locked loop circuit Gain control circuitry for delay locked loop circuit

2005-06-07

2005-06-07

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

06903586

ABSTRACT:
A delay locked loop (DLL) circuit having gain control is presented. The DLL circuit includes a bias generator responsive based on an error signal to produce first and second bias voltages to control a plurality of differential delay elements. The bias generator includes a bias current generator having a fixed voltage-controlled current source and a dynamic voltage-controlled current source to generate a bias current, and a bias voltage generator for receiving the bias current and generating first and second bias voltages. The bias generator can generate multiple current levels in different modes of operation. Each of the current levels of the bias generator allows a small range of currents and therefore small values of gain factors (KVCDL). Low KVCDLvalues leads to lower jitter and better control over feedback stability, resulting in an increase in the range of operational frequencies.

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