Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2001-08-22
2003-03-04
Ton, My-Trang Nu (Department: 2816)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S261000
Reexamination Certificate
active
06529077
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to high gain, high frequency amplifier circuits.
More particularly, this invention relates to circuits that compensate for changes and fluctuations in the gain of high gain, high frequency amplifier circuits due environmental factors such as manufacturing process, temperature, and operating conditions.
2. Description of Related Art
The basic structure of a differential amplifier well known in the art and is generally as shown in FIG.
1
. The n-type metal oxide semiconductor (NMOS) transistors M
1
and M
2
are generally coupled at their sources and connected to the current source I
B
. The drains of the NMOS transistors M
1
and M
2
are respectively connected to the equal valued load resistors RL
1
and RL
2
. The gates of the NMOS transistors Ml and M
2
are respectively connected to the input terminals IN
1
and IN
2
. The drain currents of the NMOS transistors M
1
and M
2
are summed and must be equal to the current of the current source I
B
. It can thus be shown that the voltage present at the drain of the NMOS transistors M
1
and M
2
is equal to:
V
OUTd
=−g
m
RL
n
V
lNd
where:
V
OUTd
is the differential voltage at the output nodes OUT
1
and OUT
2
.
g
m
is the transconductance of the NMOS transistors M
1
and M
2
.
RL
n
is the resistance of the resistors RL
1
or RL
2
.
V
INd
is the differential voltage at the input nodes IN
1
and IN
2
.
The variations in the differential voltage V
OUTd
due to variations in the environmental factors such as temperature, process parameters, and operating conditions can be shown to effect the values of the transconductance gm of the NMOS transistors M
1
and M
2
and the dependence of the resistors RL
1
and RL
2
to the environmental factors. One method for compensation of these variations is to place the source degeneration resistors Rs
1
and Rs
2
respectively in the source connections of the NMOS transistors M
1
and M
2
. The source degeneration resistors Rs
1
and Rs
2
have resistance designs to sufficiently improve the immunity of the differential amplifier to the variations, but not impact the dynamic range of the output voltage V
OUTd
.
The effective transconductance g
ms
of the NMOS transistors M
1
and M
2
in combination with the source degeneration resistors Rs
1
and Rs
2
can be shown to be equal to:
g
ms
=
g
m
1
+
g
m
Rs
Eq
.
1
Further, the gain of the differential amplifier is then expressed as:
Av
=
V
OUTd
V
INd
=
g
ms
RL
n
Eq
.
2
As is known the appropriate choices of the materials for the resistors Rs
1
and Rs
2
and the resistors RL
1
and RL
2
minimize the effects of the environmental factors. However, this does not stabilize the gain completely.
As the gain requirements for an amplifier increases, multiple differential amplifiers of
FIG. 1
are cascaded as shown in FIG.
2
. The first differential stage Av
1
of the cascaded amplifier is formed of the NMOS transistors M
20
and M
21
, the load resistors RL
3
and RL
4
, the current source I
B1
, and the source degeneration resistors Rs
1
and Rs
2
configured as shown in FIG.
1
. The second differential stage Av
2
of the cascaded amplifier is formed of the NMOS transistors M
22
and M
23
, the load resistors RL
5
and RL
6
, the current source I
B2
, and the source degeneration resistors RS
3
and Rs
4
, also configured as shown in FIG.
1
. Similarly, the third differential stage AV
3
of the cascaded amplifier is formed of the NMOS transistors M
24
and M
25
, the load resistors RL
7
and RL
8
, the current source I
B3
, and the source degeneration resistors Rs
5
and Rs
6
, which are configured as shown in FIG.
1
. The input nodes IN
1
and IN
2
are coupled by capacitors C
P1
and C
P2
to the gates of the NMOS transistors M
20
and M
21
. The bias resistors R
B1
and R
B2
provide a biasing voltage from the biasing voltage power supply V
GG
to bias the amplifier Av
1
to operate in a linear, high gain region. The output terminals of the amplifier Av
1
are coupled through the capacitors C
P3
and C
P4
to the gates of the NMOS transistors M
22
and M
23
. As described for the bias resistors R
B1
and R
B2
, the bias resistors R
B3
and R
B4
provide a biasing voltage from the biasing voltage power supply V
GG
to bias the amplifier Av
2
to operate in a linear, high gain region. Next, the output terminals of the amplifier Av
2
are coupled through the capacitors C
P5
and C
P6
to the gates of the NMOS transistors M
24
and M
26
. As described for the bias resistors R
B1
and R
B2
and the bias resistors R
B3
and R
B4
, the bias resistors R
B5
and R
B6
provide a biasing voltage from the biasing voltage power supply V
GG
to bias the amplifier Av
3
to operate in a linear, high gain region. The output signal of the amplifier is coupled through the capacitors C
P7
and C
P8
to the output terminals OUT
1
and OUT
2
. The gain of the amplifier of
FIG. 2
is the product of the individual gains of the differential amplifier stages Av
1
, Av
2
, and Av
3
and are determined as defined above for the amplifier described in FIG.
1
. Further, the number of differential amplifier stages Av
1
, Av
2
, and Av
3
is determined by the total gain required for the amplifier, thus the design of the individual stages may vary to accommodate the design requirements.
As described above the source degeneration resistors Rs
3
Rs
4
, Rs
5
and Rs
6
, Rs
7
and Rs
8
are added to partially compensate for the variations in the environmental factors. Further, other compensation techniques employ feedback to adjust the gain of the differential amplifier stages with changes in the environmental factors. However, feedback techniques do not work well when very large gain factors are required for the amplifier. In Analog Integrated Circuit Design, Johns and Martin, John Wiley & Sons, Inc., New York, 1999, pp. 248-251, the author notes that the transconductance of the NMOS transistors of a differential amplifier is the most important parameter to stabilize. The authors detail and analyze basic techniques to prevent variations of the transconductance with variations in the environmental factors.
U.S. Pat. No. 6,018,270 (Stuebing, et al.) describes a single biasing circuit for a single or multiple stage low voltage RF circuits including one or more amplifiers and one or more single or double balanced mixers. The biasing circuit incorporates compensation for temperature and integrated circuit process parameters.
U.S. Pat. No. 4,409,558 (Knijnenburg, et al.) describes a gain compensated transistor amplifier arrangement for use in power protection circuits. The amplifier includes an emitter-follower transistor. The collector current of the emitter-follower transistor is fed to a resistor to compensate for variations in the current gain factor of the transistors of the amplifier.
U.S. Pat. No. 4,916,407 (Olver) illustrates a gain variation compensating circuit for a feed-forward linear amplifier. The gain compensating circuit counteracts the gain variations and restores balance and fundamental cancellation to the circuit while retaining the highly linear characteristics of the amplifier.
U.S. Pat. No. 5,274,339 (Wideman, et al.) teaches circuit for compensating for GaAs FET amplifier gain variations over a frequency band as a function of temperature. The circuit includes a passive equalizer circuit having a fixed gain over the frequency band and an active equalizer circuit, in series with the passive equalizer, having a gain, which varies over the frequency band as a function of temperature.
U.S. Pat. No. 6,046,642 (Brayton, et al.) describes an active bias compensation circuit that senses a quiescent current flowing in an amplifier and adjusts the quiescent current to maintain an optimal DC biasing of the amplifier over a wide range of temperature variation, process variation, history of the amplifier, etc.
U.S. Pat. No. 5,673,047 (Moreland) describes a gain compensating difterential reference circuit that is used to match the gain of an inpu
Ackerman Stephen B.
Institute of Microelectronics
Knowles Billy
Nu Ton My-Trang
Saile George O.
LandOfFree
Gain compensation circuit for CMOS amplifiers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Gain compensation circuit for CMOS amplifiers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gain compensation circuit for CMOS amplifiers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3033467