Gain cell memory having read cycle interlock

Details Gain cell memory having read cycle interlock Gain cell memory having read cycle interlock

2005-09-20

2005-09-20

Phan, Trong (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S203000

Reexamination Certificate

active

06947348

ABSTRACT:
A method is provided for accessing a storage cell of a dynamic random access memory (DRAM) having an array of gain cells being read accessible by a read wordline and a read bitline, and being write accessible by a write wordline and write bitline separate from said read wordline and read bitline. The method includes activating a read wordline of the array of gain cells to permit signals from a plurality of gain cells coupled to the read wordline to develop on a plurality of corresponding read bitlines coupled to the gain cells. An interlock signal is then generated in the DRAM after activating the read wordline. The read wordline is then deactivated in response to the interlock signal.

REFERENCES:
patent: 5054002 (1991-10-01), Ninomiya et al.
patent: 5903505 (1999-05-01), Wik et al.
patent: 6151266 (2000-11-01), Henkels et al.
patent: 6385122 (2002-05-01), Chang
patent: 6577530 (2003-06-01), Muranaka et al.

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