Gain and error correction circuitry

Details Gain and error correction circuitry Gain and error correction circuitry

2000-05-03

2001-02-20

Lee, John R. (Department: 2878)

Radiant energy

Photocells; circuits and apparatus

Photocell controlled circuit

C327S514000

Reexamination Certificate

active

06191412

ABSTRACT:

BACKGROUND INFORMATION
This invention is generally related to analog signal processing and more particularly to gain and error correction in analog storage circuits.
Analog storage circuits are commonly used to store different types of analog information. For example, an image sensor can be viewed as a type of analog storage circuit which provides signals representing light intensity. The image sensor contains an array of photocells that are electrically responsive to incident light. The photocell through readout circuitry provides an output signal that represents a light-generated signal inside the photocell.
One of the tasks for using analog storage arrays is to faithfully read the stored information. The task becomes particularly difficult for larger and denser arrays in which the smaller size of the individual cells restricts the range of circuits that can be used as readout circuitry in each cell.
For example,
FIG. 1
illustrates in relevant part a typical compact prior art photocell
104
. The cell
104
using only a few MOS circuit elements, such as the field effect transistor (FET), operates as described below.
The following short cuts are used in this disclosure to describe various operating regions of the MOS field effect transistor (FET). An FET is said to be “turned off” when V
GS
(gate-source voltage) ≦V
T
(threshold voltage) for the device and the device is operating in the cut-off region where its channel acts as an open circuit. When a FET is “turned on”, V
GS
>V
T
, V
DS
(drain-source voltage) is normally small and the device is operating in the non-saturation region.
The cell
104
operates in response to RESET and SAMPLE signals being used to turn on M
13
and M
14
which causes the voltage at node A (V
IN
) to rise to a reset value. When the desired object or scene comes into view of the image sensor containing the cell
104
, a timer (exposure timer, not shown) is triggered and M
13
is turned off. Thereafter, photo-generated electron-hole pairs in photodiode D
10
cause a photocurrent (light-generated signal) Iphoto which discharges the capacitor C
10
through M
14
and consequently results in V
IN
decaying. When the timer runs out, M
14
is turned off, leaving an exposed value for V
IN
on C
10
. M
14
thus acts as an electronic shutter in limiting the light energy detected by the pixel. The difference between the reset value of V
IN
and the exposed value, together with the exposure or “integration” time defined by the timer, gives a measure of the incident light energy detected by the pixel.
To read the light intensity information in V
IN
, the prior art cell
104
includes readout circuitry having M
11
and M
12
. M
11
is used as an amplifier whereas M
12
is a switch. The readout circuitry together with a load (provided external to the cell, but not shown) on node B form an amplifier in a source follower configuration having a voltage gain less than one but a current gain greater than one when a SELECT signal is applied that turns on M
12
. When that happens, an analog signal V
OUT
representative of V
IN
(and hence the information stored in the cell), may be read from the cell. An example of an active pixel (photocell) with associated readout circuitry is discussed in U.S. Pat. No. 5,471,515, “Active Pixel Sensor With Intra-Pixel Charge Transfer,” to Fossum et al.
For a cell having ideal read-out circuitry, V
OUT
will equal V
IN
(voltage gain of exactly one) for the entire range of V
IN
. However, for an actual prior art cell such as cell
104
, V
OUT
is a non-linear function of V
IN
. Any non-linearity or deviation from the ideal presents an additional problem for the system designer to deal with, as the detected information deviates from the actual information.
The non-linearity in V
OUT
is known as gain distortion and may be caused by V
T
modulation, where the gain of M
11
in the readout circuitry is modulated in response to a changing threshold voltage V
T
of M
11
. This occurs because M
11
is implemented as a n-channel FET in a P-substrate, where the P-substrate is connected to zero potential or ground. The source to substrate (bulk) voltage for M
11
in this configuration is non-zero and changing for different values of V
OUT
. As a result, V
T
for M
11
, and therefore the gain of M
11
, is changing as a function of V
OUT
.
The prior art cell
104
also suffers from reduced dynamic range, due to the source follower configuration of the readout circuitry which cannot provide voltage gain per se. This is because V
OUT
is derived from the voltage at the source node of M
11
, which voltage is always smaller than V
IN
being the gate voltage of M
11
. The lower dynamic range is particularly a problem at the low end where V
IN
approaches 1 volt, as V
OUT
cannot follow such low input voltages due to the gate-source drop across M
11
and the drain-source drop across M
12
.
In addition to gain distortion and reduced dynamic range discussed above, the output signals of cells in a large array, particularly an imaging array having hundreds of thousands of cells, are susceptible to errors (small differences between design and actual values). These may be caused by manufacturing variations among the many cells in the array, and by readout noise originating in the signal path beyond the source node of M
11
.
In view of the above, it would be desirable to have a circuit which may correct for some or all of the above disadvantages that exist in analog storage circuits, and particularly in photocells.
SUMMARY
The invention in one embodiment is directed at a circuit having first and second portions coupled together at an intermediate node. The first portion has at least one first device that is a replicate of a second device in the second portion. The second portion is configured to provide an output signal that is linearly proportional to an input signal received by the first portion in response to the first and second devices conducting substantially the same amount of current.


REFERENCES:
patent: 5471515 (1995-11-01), Fossum et al.
patent: 5877715 (1999-03-01), Gowda et al.
patent: 6093924 (2000-07-01), Afghahi
J.E.D. Hurwitz, P.B. Denyer, D.J. Baxter, and G. Townsend, “An 800K-Pixel Color CMOS Sensor for Consumer Still Cameras,” SPIE vol. 3019 (1997), pp. 115-124.
S.K. Mendis, S.E. Kemeny, R.C. Gee, B. Pain, Q. Kim, and E.R. Fossum, “Progress in CMOS Active Pixel Image Sensors,” SPIE vol. 2172 (1994), pp. 19-29.

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