Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
1999-08-10
2001-08-21
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S155000
Reexamination Certificate
active
06278392
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to gain adjustable systems and more particularly to gain adjustable sigma delta modulator systems.
As is known in art, gain adjustable systems have a wide range of application. One such application is as in a multiplying circuit, such as in power measuring. Many such systems use digital circuitry in such application. One application is for use in watt-hour meters. One example of a watt-hour meter that multiplies two one-bit digital data streams is disclosed in European Patent Application 90313050 to The General Electric Company. One of the two one-bit digital data streams is representative of the current supplied to a load and the other of the two one-bit digital data streams is representative of the voltage across the load. In the disclosed watt-hour meter, an accumulator is used to accomplish the multiplication of the two data streams and to generate an output signal having a pulse rate that is representative of the power supplied to the load.
Another example of a power meter that multiplies two time varying signals is disclosed in an article entitled “A Power Meter ASIC With a Sigma-Delta-Based Multiplying ADC” by F. Op 't Eynde, published in the ISSCC94 Proceedings, paper TP 11.1. In the system disclosed by Eynde, a one-bit data stream from a sigma delta modulator is multiplied in the analog domain with a second input time varying signal. The resulting product is digitized using a second sigma-delta modulator. Since the multiplication in the Eynde system is accomplished in the analog domain, the system suffers from the same drawbacks as the analog multipliers discussed above.
SUMMARY OF THE INVENTION
In accordance with one feature of the invention, a system is provided having an adjustable gain. The system includes: a modulator for producing a stream of digital words representative of an input analog signal; and, a gain adjustor fed by a gain signal representative of the adjustable gain for converting the stream of digital words produced by modulator into an output stream of digital words representative of the gain adjusted input analog signal.
With such an arrangement, the stream of digital words produced by modulator, which represent the gain adjusted input analog signal, can be produced with a register for storing the gain signal and an adder. Further, the stream of digital words produced by modulator can be fed to an compact sinc filter for conversion into digital words which represent digital samples of the gain adjusted input analog signal.
In accordance with another feature of the invention, a system is provided having a sigma-delta modulator for producing a stream of digital words having values, M or N, such stream of digital words being representative of an input analog signal, X(t) fed to the modulator. A gain adjustor is fed by the sigma-delta modulator and a gain signal representative of the variable gain. The gain adjustor converts the stream of digital words produced by sigma delta modulator into an output stream of digital words having values P or Q, where P=M−(G−1)/2 and Q=N+(G−1)/2, such output stream of digital words representing an output analog signal Z(t)=GX(t).
In accordance with another feature of the invention, a multiplying circuit is provided. The multiplying circuit includes a first analog to digital converter fed by a first analog signal, for converting such first analog signal into a corresponding, gain adjusted, digital signal. The first analog to digital converter includes: a sigma-delta modulator for converting such first analog signal into a series of digital words; a gain adjustor, fed by a signal representative of an adjustable gain, for converting such series of digital words into a gain adjusted series of digital words; and a filtering section for converting the gain adjusted series of digital words into a corresponding output of digital words, each one of the output digital words representing a gain adjusted sample of the first analog signal. A second analog to digital converter is provided for converting a second analog signal into a corresponding digital signal. A multiplier multiplies the output digital words produced by the filtering section with the digital signal produced by the second analog to digital converter.
In accordance with one embodiment of the multiplying circuit, the second analog to digital converter converts the second analog signal into a corresponding stream of digital words.
In accordance with another feature of the multiplying circuit, the stream of digital words produced by the second analog to digital converter is multiplied by the output digital words produced by the filtering section in the multiplier.
In accordance with another feature of the invention, the filtering section has a sync filter.
In accordance with another feature of the invention, the multiplying circuit includes a second subtractor for subtracting the mean of the values representing the stream of digital words produced by the sigma delta modulator from the output digital words produced by the filtering section.
In accordance with another aspect of the invention, a method is provided for adjusting gain provided to an input analog signal. The method includes: producing a stream of digital words representative of the input analog signal; and converting the stream of digital words into an output stream of digital words representative of a gain adjustable input analog signal.
In accordance with one embodiment of the invention, the method including producing the digital words in the output stream of bits with the same mean as the digital words in the stream of digital words representative produced by the sigma delta modulator.
REFERENCES:
patent: 4851841 (1989-07-01), Sooch
patent: 5134401 (1992-07-01), McCartney et al.
patent: 5862069 (1999-01-01), Nestler
patent: 5995036 (1999-11-01), Nise et al.
patent: 6061008 (2000-05-01), Abbey
patent: 6081565 (2000-06-01), Marandi et al.
patent: 6154161 (2000-11-01), Leme et al.
“A Power Meeting ASIC With a Sigma-Delta-Based Multiplying ADC” by F.Op't Eynde; 1994 IEEE International Solid-State Circuits Conference; pp. 186 & 187.
Analog Devices Inc.
Jean-Pierre Peguy
Samuels , Gauthier & Stevens, LLP
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