GaAs plannar diode and manufacturing method therefor

Details GaAs plannar diode and manufacturing method therefor GaAs plannar diode and manufacturing method therefor

1987-10-22

1989-03-21

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437027, 437061, 437904, H01L 21265, H01L 2991

Patent

active

048142840

ABSTRACT:
A GaAs planar diode includes an N type GaAs substrate having an N.sup.+ GaAs layer on which an N.sup.- GaAs layer is formed. A first impurity layer of the N.sup.+ type is formed on the N.sup.31 GaAs layer. A second impurity layer of a p.sup.+ type is formed on the first impurity layer, wherein a p-n junction is formed between the first and second impurity layers. A semi-insulation region, for encompassing a predetermined area of the p-n junction of the first and second impurity layers, is formed in the substrate. The depth of the semi-insulation region in the substrate is deeper than the total depth of the first and second impurity layers, so that the semi-insulation region serves as an element isolation region of the p-n junction of the first and second impurity layers.

REFERENCES:
patent: 3986192 (1976-10-01), Di Lorenzo et al.
patent: 4064620 (1977-12-01), Lee et al.
patent: 4381952 (1983-05-01), Rosen
patent: 4728616 (1988-03-01), Ankri et al.
D'Avanzo, "Proton Isolation for GaAs Integrated Circuits," IEEE Transactions on Electron Devices, vol. 29, No. 7, p. 1051, Jul. 1982.

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