GaAs FET manufacturing process employing channel confining layer

Details GaAs FET manufacturing process employing channel confining layer GaAs FET manufacturing process employing channel confining layer

1988-12-06

1990-10-09

Hearn, Brian E.

Fishing, trapping, and vermin destroying

148DIG15, 148DIG84, 148DIG105, 148DIG141, 357 232, 357 15, 437 26, 437 29, 437 39, 437176, 437912, H01L 21265, H01L 2144

Patent

active

049620509

ABSTRACT:
A high speed GaAs FET is provided by forming a sandwiched GaAs channel between AlGaAs layers and employing an Si implant to provide channel doping for the GaAs channel. The poor activation efficiency of Si in AlGaAs relative to its activation efficiency in GaAs provides a channel having a higher active dopant concentration than exists in the adjacent sandwiching layers. This tends to enhance conductivity in the channel relative to the sandwiching layers.

REFERENCES:
patent: 4593301 (1986-06-01), Inata et al.
patent: 4605945 (1986-08-01), Katayama et al.
patent: 4727403 (1988-02-01), Hida et al.
patent: 4792531 (1988-12-01), Kakihana
patent: 4806998 (1989-02-01), Vinter et al.
Geissberger et al., "Refractory Self-Aligned Gate Process . . . ", IEEE International Microwave Symposium Digest, 1987-MTT-S, pp. 665-668.

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