GAAS FET logic having increased noise margin

Details GAAS FET logic having increased noise margin GAAS FET logic having increased noise margin

1987-04-30

1989-01-17

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307448, 307475, H03K 19094

Patent

active

047989785

ABSTRACT:
A high performance logic family for GaAs Enhancement/Depletion mode MESFETs is disclosed. The inventive logic family exhibits a large noise margin with little sacrifice in speed/power performance.

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Steven L. Long et al., "High Speed GaAs Integrated Circuits", Proc. of the IEEE, vol. 70, No. 1, Jan. 1982.
K. Suyama et al., "Design and Performance of GaAs . . . ", Proc. of the IEEE on El. ev. vol. ED27, No. 6, Jun. 1980.
Lehovec et al, "Analysis of GaAs FET's for Integrated Logic", IEEETELD, vol. ED-27, No. 6, 6-1980, pp. 1074-1091.

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