GaAs Complementary enhancement mode junction field effect transi

Details GaAs Complementary enhancement mode junction field effect transi GaAs Complementary enhancement mode junction field effect transi

1984-01-16

1986-02-04

Edlow, Martin H.

357 42, 357 51, 357 91, H01L 2980

Patent

active

045689571

ABSTRACT:
Ultra low-power GaAs complementary junction field effect transistors are implemented in the design of complementary integrated circuits using a planar technology in conjunction with multiple and selective ion implantation. Both junction FETs, namely the p and n channel devices, are enhancement mode devices and biased in the forward direction thus leading to the advantageous DCFL (directly coupled field effect transistor logic) with one power supply, low power dissipation and high packing densities, all prerequisites for VLSI (very large scale integration).

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K. Lehovec and R. Zuleeg, "Analysis for GaAs FETs for Integrated Logic," IEEE Trans. Electron Devices (Special Issue), vol. ED-27, pp. 1074-1091, Jun. 1980.
Y. Kato, et al., "GaAs MSI with JFET DCFL," in 1983 GaAs IC Symp., Tech. Dig., pp. 182-185.
G. L. Troeger and J. K. Notthoff, "A Radiation-Hard, Low-Power GaAs Static RAM Using E-JFET DCFL," in 1983 GaAs IC Symp. Tech. Dig., Paper 20.
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R. Zuleeg, et al., "Femtojoule High-Speed Planar GaAs E-JFET Logic," IEEE Trans. Electron Devices, vol. ED-25, pp. 628-639, Jun. 1978.

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