Ga/As NOR/NAND gate circuit using enhancement mode FET's

Details Ga/As NOR/NAND gate circuit using enhancement mode FET's Ga/As NOR/NAND gate circuit using enhancement mode FET's

1982-12-15

1985-05-21

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307450, 307550, H03K 19003, H03K 19094, H03K 1920

Patent

active

045188718

ABSTRACT:
In an integrated logic circuit employing normally-off type FET's, it is difficult, but desirable to realize a NAND gate due to unwanted flow of the forward current to the next stage.
In accordance with the invention, a stable NAND gate operation can be realized by introducing a NOR gate into all gate electrodes of the inputs of the NAND gate, except one gate electrode thereof of which source is grounded.

REFERENCES:
patent: 4038563 (1977-07-01), Zuleeg et al.
patent: 4405870 (1983-09-01), Eden
patent: 4417162 (1983-11-01), Keller et al.
IEEE Trans Electron Device, vol. ED-27, No. 6, 1974 (1980), pp. 1074-1091, Lehovee et al., "Analysis of GaAs FET'for Integrated Logic".
Nachrichtentechnik Elektronik, vol. 31, No. 2, J. Herzog, "Monolithisch Galliumarsenid-Basis, Teil 1,", pp. 48-52.

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