Fused multiply-add rounding and unfused multiply-add...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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C708S523000

Reexamination Certificate

active

08046399

ABSTRACT:
A computer processor including a single fused-unfused floating point multiply-add (FMA) module computes the result of the operation A*B+C for floating point numbers for fused multiply-add rounding operations and unfused multiply-add rounding operations. In one embodiment, a fused multiply-add rounding implementation is augmented with additional hardware which calculates an unfused multiply-add rounding result without adding additional pipeline stages. In one embodiment, a computation by the fused-unfused floating point multiply-add (FMA) module is initiated using a single opcode which determines whether a fused multiply-add rounding result or unfused multiply-add rounding result is generated.

REFERENCES:
patent: 6275838 (2001-08-01), Blomgren et al.
patent: 6460134 (2002-10-01), Blomgren et al.
patent: 6542916 (2003-04-01), Hinds et al.
patent: 6557021 (2003-04-01), Brooks et al.
patent: 6889241 (2005-05-01), Pangal et al.
patent: 7080111 (2006-07-01), Pangal et al.
patent: 7099910 (2006-08-01), Brooks et al.
patent: 7225323 (2007-05-01), Siu et al.
patent: 7346643 (2008-03-01), Ho et al.
patent: 7392273 (2008-06-01), Gerwig et al.
patent: 7912887 (2011-03-01), Dockser et al.
patent: 2005/0228844 (2005-10-01), Dhong et al.
patent: 2006/0179096 (2006-08-01), Fleischer et al.
A. Naini, A. Dhablania, W. James and D. Das Sarma, “1 GHz HAL Sparc64 Dual Floating Point Unit with RAS Features,” Proceedings of the 15th Symposium on Computer Arithmetic, pp. 173-183, 2001.
C. C Hinds, “An Enhanced Floating Point Coprocessor for Embedded Signal Processing and Graphics Applications,” Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, pp. 147-151, 1999.
Eric Charles Quinnell, “Floating-Point Fused Multiply-Add Architectures,” PhD Dissertation at University of Texas at Austin, May 2007.
Rarick, “Processor which Implements Fused and Unfused Multiply-Add Instructions in a Pipelined Manner”, U.S. Appl. No. 12/057,894, filed May 15, 2008.
Rarick, “Leading Zero Estimation Modification for Unfused Rounding Catastrophic Cancellation”, U.S. Appl. No. 12/121,053, filed May 15, 2008.
Schmookler et al., “Leading Zero Anticipation and Detection—A Comparison of Methods”,Proceedings of the 15thIEEE Symposium on Computer Arithmetic, 2001, pp. 7-12.

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