Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Patent
1995-05-31
1996-12-31
Ngo, Ngan V.
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
257209, 437 60, 437249, 437922, H01L 2710
Patent
active
055897061
ABSTRACT:
An improved etch behavior is promoted to generate vertical sidewalls for fuse links that will promote reliable and repeatable laser cutting of the fuse links. In one embodiment, dummy structures are added adjacent to fuse links in order to obtain the vertical sidewalls for reliable fuse deletion. The dummy structures form no part of the fuse or circuit structure but, because of the proximity of the dummy structures to the fuse links, vertical sidewalls are promoted in a reactive ion etch which is used to form the fuse array. In another embodiment, the vertical sidewalls of the fuse links are achieved in a damascene process in which grooves are formed in an oxide layer and filled with a metal. These grooves correspond to the fuse links and alternating dummy structures. Once filled, the surface is planarized using a chemical-mechanical process. The dummy structures provide reinforcement for the metallization (metal and dielectric film), maintaining the integrity of the metallization. In both embodiments, the vertical sidewalls and constant height of the resulting fuse links promote reliable laser cutting.
REFERENCES:
patent: 3959047 (1976-05-01), Alberts et al.
patent: 4853758 (1989-08-01), Fischer
patent: 5015604 (1991-05-01), Lim et al.
patent: 5017510 (1991-05-01), Welch et al.
patent: 5230772 (1993-07-01), Kadomura
patent: 5235205 (1993-08-01), Lippitt, III
patent: 5264387 (1993-11-01), Beyer et al.
patent: 5278105 (1994-01-01), Eden et al.
patent: 5317185 (1994-05-01), Fernandes et al.
patent: 5420455 (1995-05-01), Gilmour et al.
Santini et al., "Method for Improving Plating Uniformity in Micron and Submicron Thin Film Devices" IBM Technical Disclosure Bulletin vol. 27 No. 3 Aug. 1984.
Cronin et al., "Minimum Groundrule, Electrically BLown Tungsten/Aluminum Fuse by Electromigration" IBM Technical Disclosure Bulletin vol. 31, No. 5 Oct. 1988.
Craig et al., "On-Chip Elctrically Programmable Fuse" IBM Technical Disclosure Bulletin vol. 29, No. 3, Aug. 1986.
Mitwalsky Alexander
Ryan James G.
International Business Machines Corp.
Mortinger Alison D.
Ngo Ngan V.
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