Fuse layout for improved fuse blow process window

Details Fuse layout for improved fuse blow process window Fuse layout for improved fuse blow process window

1998-11-05

2000-09-19

Bowers, Charles

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Using structure alterable to nonconductive state

438601, H01L 2182

Patent

active

061210749

ABSTRACT:
A method of fabricating a fuse for a semiconductor memory, in accordance with the invention, includes the steps of forming a gate structure on a substrate including a polysilicon fuse layer and a gate cap layer disposed above the polysilicon fuse layer, forming an interlevel dielectric layer over the gate structure, depositing a dielectric layer over the interlevel dielectric layer, the dielectric layer and the interlevel dielectric layer both including a material which is selectively etchable relative to the gate cap layer and selectively etching contact holes through the dielectric layer and the interlevel dielectric layer such that at least one contact hole is formed over the gate structure and extends into the gate cap layer.

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