Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Fusible link or intentional destruct circuit
Reexamination Certificate
1999-05-27
2001-04-10
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Fusible link or intentional destruct circuit
C365S225700
Reexamination Certificate
active
06215351
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fuse-latch circuit in which, by a first and a second control signal, which are staggered over time with respect to one another, fuse information (i.e. fuse is defective or intact) can be read from a fuse into a latch element and can be stored in the latter.
In a fuse-latch circuit, it ought to be possible to store fuse information for the operation of a semiconductor component, for example of a semiconductor memory, after the fuse information has been read from the fuse in the event of the supply voltage being switched on.
2. Summary of the Invention
It is accordingly an object of the invention to provide a fuse-latch circuit which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which manages with only one global control signal in order to reduce the outlay on global wiring and to preclude the occurrence of propagation delay problems between the global control signals with respect to one another.
With the foregoing and other objects in view there is provided, in accordance with the invention, a fuse-latch circuit for a fuse, including:
a first MOS transistor having a source-drain path and formed of a conductivity type;
a second MOS transistor having a source-drain path and formed of a conductivity type that is the same as the first MOS transistor, and a fuse is to be disposed between the source-drain path of the first MOS transistor and the source-drain path of the second MOS transistor;
a latch element connected to the second MOS transistor; and
a delay element connected to the first MOS transistor, the delay element receiving only one first global initialization control signal and generating a second local control signal being staggered over time with respect to the first global initialization control signal, the first global initialization control signal and the second local control signal used for reading information corresponding to a state of the fuse and the information read from the fuse being stored in the latch element.
In the case of a fuse-latch circuit of the type mentioned in the introduction, the object is achieved according to the invention by virtue of the fact that, in addition to the first control signal, the second control signal is also obtained from a global initialization signal by the delay element.
In the fuse-latch circuit according to the invention, therefore, two essential further measures are employed in addition to the existing circuit:
(a) One of the control signals is obtained from the other, global control signal by the time delay, for which purpose inverters can advantageously be used.
(b) The fuse is connected to ground only after initialization via a switch, for example an NMOS transistor, in order to prevent a parallel-path current, which will be present in the case of an intact fuse, during initialization.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a fuse-latch circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5566107 (1996-10-01), Gilliam
patent: 5619469 (1997-04-01), Joo
patent: 5640365 (1997-06-01), Imamiya et al.
patent: 5680360 (1997-10-01), Pilling et al.
patent: 19631130A1 (1998-02-01), None
Le Thoai-Thai
Schneider Helmut
Cunningham Terry D.
Greenberg Laurence A.
Lerner Herbert L.
Siemens Aktiengesellschaft
Stemer Werner H.
LandOfFree
Fuse-latch circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fuse-latch circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fuse-latch circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2522058