Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2003-02-28
2004-10-19
Clark, S. V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S751000
Reexamination Certificate
active
06806551
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a fuse construction for integrated circuit structures. More particularly this invention relates to construction of a fuse useful in integrated circuit structures having one or more layers of low k dielectric material and optionally also containing copper interconnects.
2. Description of the Related Art
The shrinking of integrated circuits has resulted in levels of electrically conductive interconnects being placed closer together vertically, as well as reduction of the horizontal spacing between the electrically conductive interconnects, such as metal lines, on any particular level of such interconnects. As a result, capacitance has increased between such conductive portions, resulting in loss of speed and increased cross-talk. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO
2
) dielectric material, having a dielectric constant (k) of about 4.0, with another insulation material having a lower dielectric constant to thereby lower the capacitance.
In an article by L. Peters, entitled “Pursuing the Perfect Low-K Dielectric”, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a Flowfill chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U. K. The process is said to react methyl silane (CH
3
—SiH
3
) with hydrogen peroxide (H
2
O
2
) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which is annealed at 400° C. to remove moisture.
An article by S. McClatchie et al. entitled “Low Dielectric Constant Oxide Films Deposited Using CVD Techniques”, published in the 1998 Proceedings of the Fourth International Dielectrics For ULSI Multilevel Interconnection Conference (Dumic) held on Feb. 16-17, 1998 at Santa Clara, Calif., at pages 311-318, also describes the formation of methyl-doped silicon oxide by the low-k Flowfill process of reacting methyl silane with H
2
O
2
to achieve a dielectric constant of ~2.9.
The incorporation of such low dielectric constant (low k) carbon-doped silicon oxide dielectric material into interconnect architecture has been very attractive not only because of the low k properties, but also because of the compatibility with conventional silicon process technologies. Generally these materials remain stable upon annealing at temperatures of up to 500° C. Such carbon doped silicon oxide dielectric materials are characterized by the structure of amorphous silicon oxide with incorporated methyl groups and hydrogen species, and are also characterized by a reduced density in comparison with conventional silicon oxide that can be explained by the formation of microporosity surrounding the incorporated methyl groups. Furthermore, such hydrocarbon-modified silicon oxide dielectric materials deposited by CVD techniques are also characterized by strong adhesion.
However, such low k carbon-doped silicon oxide dielectric material are susceptible to deleterious reaction with moisture when the low k material is exposed to the air, such as when a via is etched through a layer of such low k dielectric material, or when a fuse, mounted on the upper surface of a layer of the low k dielectric material, is blown. The reaction materials or byproducts resulting from reaction of the low k dielectric material with moisture can result in failures in subsequent assembly processing of the integrated circuit structure.
The above-mentioned shrinking of integrated circuits and resultant increase in capacitance and loss in speed has also resulted in a renewed interest in the utilization of higher conductivity materials such as copper for via filling or for forming the metal interconnects or “wiring” used in the integrated circuit structure because of its superior electrical conductivity compared to conventional metals used for these purposes such as aluminum or tungsten. When copper is utilized for this purpose it conventionally is also used for the formation of blowable fuses as well, as a matter of process efficiency.
However, copper, like the above-discussed low k dielectric material, is also susceptible to reaction with moisture when exposed to air. In the construction of copper fuses used, for example, in ASIC (Application Specific Integration Circuits) technology, blowing of the fuse by a laser beam can result in creation of an opening or hole which can expose the remnants of the copper fuse (as well as an underlying layer of low k dielectric material) to air. The resultant reaction between the copper and the moisture in the air tends to make the copper regrow, thereby reconnecting the blown fuse and consequently, for example, causing data error in the embedded memory of an ASIC device.
It would, therefore, be desirable to provide a fuse structure and process for forming same wherein such problems can be eliminated in an integrated circuit structure which contains low k dielectric material and optionally copper metal interconnects and/or copper-filled vias as well, while still maintaining process efficiencies, thereby permitting the benefits of the use of low k dielectric materials and optionally also copper-filled vias and/or copper metal interconnects.
SUMMARY OF THE INVENTION
In accordance with the invention fuses, and optionally metal pads, are formed over a layer of low k dielectric material in an integrated circuit structure by first providing, over portions of an integrated circuit structure, a layer of low k dielectric material, the layer of low k dielectric material having first openings in an upper surface thereof lined with a first conductive barrier material and filled with a filler metal such as copper, to form metal interconnects in the upper surface of the layer of low k dielectric material; forming a first dielectric layer over the layer of low k dielectric material and over the metal interconnects in the upper surface of the layer of low k dielectric material patterning the first dielectric layer to form second openings therein communicating with the metal interconnects in the first openings in the layer of low k dielectric material; forming a second conductive barrier layer over the first dielectric layer and in contact with the metal interconnects exposed by the patterning of the first dielectric layer; patterning the second conductive barrier layer to form fuse portions between some of the metal interconnects, and to form a liner over one or more of the metal interconnects; and forming a second dielectric layer over the patterned conductive barrier metal layer to thereby form a window of second dielectric material above each of the fuse portions.
Preferably, the process includes the further steps of patterning the second dielectric layer to form a third opening over at least some of the liners of conductive barrier material over the metal interconnects; and filling the third openings with metal to form metal pads, each in electrical contact with a metal interconnect through a liner.
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Castagnetti Ruggero
Liu Yauh-Ching
Venkatraman Ramnath
Clark S. V.
LSI Logic Corporation
Taylor John P.
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