Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Fusible link or intentional destruct circuit
Reexamination Certificate
1999-07-06
2001-08-28
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Fusible link or intentional destruct circuit
Reexamination Certificate
active
06281739
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fuse circuit and redundant decoder, in particular, ones that are used for a memory device.
2. Description of the Related Art
Greatly due to the progress of microscopic process technology, the capacity of a semiconductor memory device, which is mostly represented by DRAM (Dynamic Random Access Memory), has rapidly been increasing year by year. The wiring, transistor, capacitor, etc. that composite the semiconductor memory device has been annually decreasing in size.
As a result, it is very difficult to make all semiconductor memory devices free of faulty memory elements. If a single abnormal memory element exists, the semiconductor memory device is defective, and measures must be taken to keep the yield from dropping. In order to solve this problem, a redundant circuit is generally established within the memory device.
When there is a defective memory element (a defective memory cell) in the memory device, the redundant circuit acts as a circuit which replaces it with a spare memory element (a redundant cell). As the corresponding address is entered, the defective memory element is detected and access to the element is prevented. In turn, the redundant cell is accessed, making it seem from the outside as if the defect never existed. By using the redundant circuit in this way, the semiconductor memory device, which includes some defective cells caused by product imperfections, is marketable. Therefore, the yield of the merchandise makes great strides.
As described above, the redundant circuit replaces a defective memory cell with a redundant cell. Accordingly, the redundant circuit must have the capacity to continuously monitor each of the addresses supplied from outside the semiconductor memory device, and detect the address corresponding to the defective memory cell. An example of a circuit with the above detection capacity is generally attained using a fuse-based, programmable circuit.
Japanese Patent Application Laid-open No. Hei-8-96594 discloses such a programmable circuit. In this application, the programmable circuit has two fuses for each of the bits that make up the address signal. The programmable circuit is programmed to operate in a certain circuit pattern, by cutting off either one of the two fuses. Thus, each fuse can be set up to be either conductive or not, according to the configuration of each of the bits making up the address signal. For example, when one of the bits is high level, its corresponding fuse is set to be non-conductive, whereas when it is low level, its corresponding fuse is set to be conductive. With this fuse-based configuration, an address signal, which makes all the fuses corresponding to the respective bits non-conductive, can be detected. Therefore, programming a specific address as a defective address allows its corresponding address signal to be always monitored and detected.
The system disclosed in Japanese Patent Application Laid-open No. Hei-8-96594, however, has a problem where two fuses for each of the bits making up an address signal are necessary. For example, where the address signal is made up of ten bits, twenty fuses are needed for programming a single defective address and, 2,048 fuses are needed in the semiconductor memory device with a capacity of programming 1,024 defective addresses. In this case, since each fuse has to occupy a large area on the chip, forming such a quantity of fuses in the chip requires a large chip. This is not preferable.
Accordingly, another programmable system, where only a single fuse for each of the bits making up the address signal is used, has been proposed so as to solve the above problem. In this system, each bit of a defective address is memorized as either “1” or “0” by either cutting off or not the corresponding single fuse. The initializing step, right after energizing, stores the above defective address memorized, in a volatile, holding circuit. According to this system, the number of necessary fuses are practically halved, compared to the aforementioned system, due to the fact that only a single fuse for each of the bits that make up the defective address is necessary.
However, the above system requires an additional operation such as the initializing operation, which is performed right after energizing, even though the number of fuses can be largely reduced. More specifically, the initializing operation is performed in such a manner that electric current paths are generated for the respective fuses in response to an initial signal (a reset signal), which has entered the chip. Thereafter, whether or not an electric current can flow through each fuse is detected so as to store resulting data in a volatile, holding circuit such as a flip-flop circuit. Japanese Patent Application Laid-open No. Hei-5-101673 discloses such a circuit as shown in
FIG. 18
, as an example.
In
FIG. 18
, an initializing circuit
1801
outputs a high level signal at a fixed time period during the initializing operation. (The initializing circuit
1801
outputs a low level signal for the other time period)
In the case where the fuse
1803
is cut off, the initializing circuit
1801
provides a high level signal for a contact
1800
within the device initializing time. Accordingly, a contact
1805
becomes a low level, thus turning on the p-channel MOS transistor
1802
. However, since the fuse
1803
is cut off, the level of the contact
1800
becomes low when the signal from the initializing circuit
1801
returns to the low level.
At this point, the contact
1805
becomes high level, thus turning off the p-channel MOS transistor
1802
. An output signal
1806
becomes low at the same time.
According to this circuit, even if the fuse
1803
has been insufficiently cut off using a laser, a possible electric current path through the p-channel MOS transistor
1802
is not generated due to the fact that the transistor
1802
is off.
However, in the case where the voltage of the contact
1800
is high level, with the fuse
1803
not cut off, the circuit in
FIG. 18
has a problem in that an unnecessary electric current (a leakage current) must flow through the electric current path via the high-impedance resistor
1807
and the p-channel MOS transistor
1802
. This state results from the fact that the transistor
1802
is on.
Japanese Patent Application Laid-open No. Hei-8-321197 discloses a fuse circuit as illustrated in
FIG. 19
, which completely prevents a leakage current from flowing even if the fuse is incompletely cut off.
The circuit in
FIG. 19
prevents a leakage current from flowing, which results from the fuse being incompletely cut off, by detecting the event of energizing, and also whether or not a fuse is completely cut off after the energizing has been stably made at a predetermined timing. Immediately after a power-on signal generating circuit
1900
in
FIG. 19
is stably energized and outputs a power-on signal
1905
, the other circuits detect the state of the fuse
1904
.
FIG. 20
illustrates the waveforms of respective signals in the circuit in
FIG. 19
when the circuit is energized. The power-on signal
1905
keeps on increasing in its voltage parallel to the increase in magnitude of the supply voltage VCC, until the magnitude reaches a predetermined level. When the magnitude reaches this level, the power-on signal
1905
becomes the grounded level. Upon reception of the power-on signal
1905
, a gate control circuit
1901
outputs both a pre-charging signal
1906
and a discharging signal
1907
.
The pre-charging signal
1906
increases in its voltage parallel to the increase in the voltage of the power-on signal
1905
. Next, it goes down sharply to and stays at the grounded level within a predetermined time period, t
1
, also parallel to the decrease in the voltage of the power-on signal
1905
. In the same manner, the discharging signal
1907
increases in its voltage parallel to the increase in the voltage of power-on signal
1905
. Next, it sharply goes down to and stays at the grounded level, also para
NEC Corporation
Nu Ton My-Trang
Young & Thompson
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