Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Fusible link or intentional destruct circuit
Reexamination Certificate
1999-01-07
2001-01-16
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Fusible link or intentional destruct circuit
Reexamination Certificate
active
06175261
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to integrated circuit adjustment structures and methods, and more particularly relates to fuse circuits for making on-chip adjustments.
BACKGROUND OF THE INVENTION
In integrated circuit design the provision of adjustment capability, or trimming, is often desirable or even needed. For example, in a computer hard drive (“HDD”) read channel integrated circuit, the cutoff frequency of the continuous time low pass filter, the free running center frequency of the time recovery voltage controlled oscillators, and various DC offsets may be advantageously centered by blowing fuses.
Fuses may be used to switch in additional unit capacitances in a capacitor bank as needed based on the particular process run and as determined by functional measurement at wafer probe or during final test. Alternatively, the value of a transconductance can be trimmed to account for the process variation in capacitors. For example, the reference current used in the transconductance control loop can be scaled up or down by means of a fusible digital to analog converter (“DAC”) to provide the proper compensation for the deviation in capacitors.
Another application for fuses is in the correction of unavoidable DC offsets, which if allowed to build up can severely degrade the performance of analog cells. In some cases, offset-correction loops or auto-zero techniques are not desirable/possible and a one time offset-correction trim is done instead at wafer probe or final test. Fuses, which control currents in a DAC, can be blown and these currents can be injected into certain nodes of the analog circuit in such a way that they counteract the offset.
The foregoing is a description of exemplary uses for fuses. Those skilled in the art understand that fuses are used for many other purposes beyond those described herein.
The various prior art fuse schemes have limitations and problems that it would be desirable to overcome. For example, as alluded to above, in prior art schemes fuses are typically blown as determined by functional measurement at wafer probe. Subsequent packaging, however, may stress the chip such that optimal fuse compensation may change.
In addition, the supply voltage must be raised to blow fuses, typically, and this puts other low voltage process circuitry at risk of damage. Further, the resistance remaining in a path after a fuse is blown may be lower than desired. After a fuse is blown, a DC current is typically forced through the fuse. With a lower than desired resistance in the fuse power consumption may be unacceptably large during evaluation. To overcome this the resistance requirement placed on a blown fuse may be made quite large, resulting in a high number of rejected parts after attempted fuse blowing.
In addition, the continuous current flow through the fuse may result in regrowth of the fuse, causing the resistance of the fuse to lower still further. This may bring the fuse to the point where the voltage drop across it during operation is at or close to the transition voltage between a blown and un-blown indication. The read state of the fuse may thus fluctuate between blown and un-blown, rendering it unstable in use. In some applications this could be highly objectionable. For example, for fuses used to trim parameters in an HDD read channel a stable, but incorrect fuse reading might be more tolerable than a fuse reading varying between blown and un-blown, since the channel may adapt other parameters during operation to partially compensate for an incorrect fuse state and provide acceptable performance. However, an unstable fuse, changing its read state between blown and un-blown may cause the read channel to continually adapt and re-adapt to the changing channel configuration created by the unstable fuse.
Therefore, it would be desirable to have a fuse circuit that permits the blowing of the fuse on-chip, i.e., after packaging. It would be desirable to have a fuse circuit suitable for low voltage processes. It would be desirable to have a fuse circuit that provides protection for other circuitry when the supply voltage is raised to blow the fuses. It would be desirable to have a fuse circuit providing more certainty regarding the remaining resistance after blowing of the fuse. It would be desirable to have a fuse circuit requiring lower power consumption and preventing regrowth of a blown fuse.
The present invention overcomes the foregoing limitations and problems.
SUMMARY OF THE INVENTION
The present invention provides, according to one aspect, an on-chip fuse circuit. The circuit includes a fuse capable of being blown during a programming operation, as well as output logic for determining whether the fuse is blown. A protection circuit is provided for protecting the output logic during programming. An evaluation circuit is provided, for evaluating whether the fuse is blown. The evaluation circuit includes a first current source coupled to the fuse, providing a first predetermined current so as to activate the output logic to read out the condition of the fuse during normal operation. It also includes a second current source coupled to the fuse, providing a second predetermined current, substantially less than the first predetermined current. The second predetermined current activates the output logic to read out the condition of the fuse during an evaluation mode such that a blown condition is indicated by the output logic only if the resistance of the fuse is substantially greater than that required for the output logic to indicate a blown condition during normal operation.
According to another aspect of the invention there is provided an on-chip fuse circuit including a first fuse and a second fuse, both being capable of being blown during a programming operation. Output logic is provided for determining whether the fuse is blown, the output logic including first indication logic for indicating whether both of the fuses are blown, during an evaluation mode, and second indication logic for indicating a blown state of the fuse circuit if either of the fuses is blown. A protection circuit is provided for protecting the output logic during programming. Finally, an evaluation circuit is provided for evaluating whether the fuse is blown.
These and other aspects and features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.
REFERENCES:
patent: 5404049 (1995-04-01), Canada et al.
patent: 5514980 (1996-05-01), Pilling et al.
patent: 5767732 (1998-06-01), Lee et al.
patent: 5838076 (1998-11-01), Zarrabian et al.
patent: 6014052 (2000-01-01), Coupe, II
patent: 6060899 (2000-05-01), Hamada
Deveirman Geert
McNutt Michael
Standiford Jay
Sundararaman Rajagopal
Willard Simon
Brady III Wade James
Moore J. Dennis
Nu Ton My-Trang
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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