Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2004-01-06
2004-10-26
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257SE23149, C438S132000
Reexamination Certificate
active
06809397
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices and, more particularly, to integrated circuit devices having fuse boxes.
BACKGROUND OF THE INVENTION
The manufacturing process of integrated circuit devices typically includes both a fabrication process and an assembly process. The fabrication process may include repeatedly forming predetermined circuit patterns on a substrate, for example, a silicon (Si) substrate, to produce a cell, for example, a memory cell. These cells are typically packaged during the assembly process, i.e. multiple cells are packaged in a single chip.
Between the fabrication process and the assembly process, an electrical die sorting (EDS) process may be performed to detect certain electrical proprieties of the cells formed on the substrate. The EDS process may indicate whether or not the cells formed on the substrate have adequate electrical properties. If it is determined that a cell formed on the substrate has inadequate electrical properties, the poor electrical properties may be removed during the EDS process before the assembly process is performed. The removal of cells having poor electrical properties before assembly of the packages may reduce manufacturing costs and simplify the assembly process.
In particular, the EDS process typically comprises a pre-laser test step, a repairing step and a post-laser test step. Data is generated with respect to the cells formed on the substrate during the pre-laser test step. Poor cells are located using the generated data and the reparable poor cells are repaired on the basis of the generated data during the repairing step. Finally, the repaired cells are retested during the post-laser test step to determine if the cells have actually been repaired.
During the repairing step of the EDS process, wirings connected to the poor cells may be cut by the irradiation of a laser, and the poor cells that are located are replaced with redundancy cells provided on the chip for this purpose. The wiring that is cut during the irradiation of the laser is a fuse of the integrated circuit device. The region of the integrated circuit device including the fuse and the portion of the integrated circuit device enclosing the fuse is a fuse portion of the integrated circuit device. The fuse portion of the integrated circuit device may include a fuse line, e.g. a portion of a bit line of the integrated circuit device that is cut by the irradiation of the laser. A fuse opening may be formed over the fuse line by etching an insulating interlayer and a passivation layer. The fuse line may be cut by, for example, irradiating a laser onto the fuse line through the fuse opening. Fuses and issues related thereto are discussed in U.S. Pat. No. 6,714,753 to Wen-Shiang Liao and U.S. Pat. No. 6,284,575 to Suk-Soo Kim, the disclosures of which are hereby incorporated herein by reference as if set forth in full.
The insulating layer generally includes an insulation material, for example, silicon oxide. In particular, the insulating layer may include an insulation material having a good step coverage, for example, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), spin-on-glass (SOG) or tetraethyl orthosilicate (TEOS), in order to reduce a step in a cell array region. When an insulating layer includes an insulation material including impurities, the interlayer dielectric may become sensitive to moisture.
Accordingly, a reliability test may be performed on the integrated circuit device under a high moisture content, a high temperature and/or a high pressure to determine whether or not the integrated circuit device can operate under these circumstances. If moisture permeates into the integrated circuit device through the insulating layer, the reliability of the integrated circuit device may be reduced because the moisture may influence the integrity of the metal wirings positioned around the fuse portion of the integrated circuit device.
To address the influence of moisture on the integrated circuit device, rectangular shaped guard rings that include metal around a fuse opening of a fuse portion of an integrated circuit device have been provided. This technique is discussed, for example, in Japanese Patent Laid-Open Publication No. 1997-69571 and will be discussed further below with respect to
FIGS. 1 and 2
.
Referring now to
FIGS. 1 and 2
, a cross-sectional view and a plan view illustrating integrated circuit devices having rectangular shaped guard rings around a fuse opening as described in the Japanese Patent Publication set out above will be described. As illustrated in
FIGS. 1 and 2
, a field oxide layer
2
is formed on an integrated circuit substrate
1
to define a cell region of an integrated circuit device. A fuse portion is formed on the field oxide layer
2
. In particular, a polysilicon wiring layer
3
is formed on the field oxide layer
2
and functions as a bit line. A first interlayer dielectric (insulating layer)
4
of, for example, silicon oxide, is formed on the polysilicon wiring layer
3
to cover the polysilicon wiring layer
3
. An opening
5
is formed on the first interlayer dielectric
4
and partially exposes the polysilicon wiring layer
3
.
A polysilicon layer is formed in the opening
5
and on the first interlayer dielectric
4
and is patterned to form a polysilicon layer pattern
6
that connects one portion of the remaining polysilicon wiring layer
3
to another portion of the remaining polysilicon wiring layer
3
. A first silicon oxide film
16
is formed on the polysilicon layer pattern
6
and the first interlayer dielectric
4
. A polysilicon layer
15
is formed on the first silicon oxide film
16
to cover the fuse portion. The polysilicon layer
15
functions as an etch stop layer of the integrated circuit device and is simultaneously formed when an upper electrode of a capacitor of the integrated circuit device is formed.
A second silicon oxide film
7
is formed on the polysilicon layer
15
and the first silicon oxide film
16
, and a planar second interlayer dielectric
8
is formed on the second silicon oxide film
7
using a material having a good fluidity, for example, BPSG After a rectangular ring shaped first opening
17
enclosing the fuse portion is formed in the second interlayer dielectric
8
, a metal layer is formed on the surface of the second interlayer dielectric
8
and in the first opening
17
. The metal layer includes, for example, aluminum, and is formed by, for example, a sputtering process. The obtained metal layer is patterned to form a first metal wiring
9
in a cell region of the integrated circuit substrate
1
, and a lower guard ring
50
in the fuse portion of the integrated circuit substrate
1
. The lower guard ring
50
includes a first lower metal layer
25
in the first opening
17
, and a first upper metal layer
20
disposed on the first opening
17
.
A third interlayer dielectric
21
that includes, for example, silicon oxide, is formed on the second interlayer dielectric
8
to cover the first metal wiring
9
and the first upper metal layer
20
. A rectangular ring shaped second opening
22
exposing the lower guard ring
50
is formed on the third interlayer dielectric
21
. A metal layer is formed on the surface of the third interlayer dielectric
21
using, for example, aluminum and a sputtering process. A metal layer is formed in the second opening
22
and patterned to form a second metal wiring
27
in the cell region of the integrated circuit substrate l, and an upper guard ring
60
in the fuse portion. The upper guard ring
60
includes a second lower metal layer
26
in the second opening
22
, and a second upper metal layer
23
disposed on the second opening
22
.
A photo resist pattern (not shown) that exposes the fuse portion is formed on a passivation film
10
after the passivation film
10
is formed on the resultant structure of the integrated circuit substrate
1
. The third interlayer dielectric
21
and the second interlayer dielectric
8
are successively etched by using the photo resist patt
Ho Tu-Tu
Myers Bigel Sibley & Sajovec P.A.
Nelms David
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