Functionally complete family of self-timed dynamic logic circuit

Details Functionally complete family of self-timed dynamic logic circuit Functionally complete family of self-timed dynamic logic circuit

1991-04-12

1993-05-04

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, H03K 19017

Patent

active

052084906

ABSTRACT:
A logic system uses novel mousetrap logic gates which implement novel vector logic. In a vector logic system, any number of valid vector logic states and one invalid vector logic state is defined by the logic signals on a set of logic paths. An invalid vector logic state is defined as the case when all logic paths exhibit a low logic signal. A valid vector logic state can be defined in a variety of ways. In the preferred embodiment, a valid vector logic state is defined as the case when one and only one of said logic paths exhibits a high logic signal. Furthermore, mousetrap logic gates, which can be connected directly in series and/or parallel to collectively perform logic functions, implement the foregoing logic scheme. Each mousetrap logic gate has an arming mechanism, ladder logic, and a buffer. A precharge is supplied by the arming mechanism to the buffer. Incoming logic is operated upon by the ladder logic and used to trigger the precharged buffer. Each of the mousetrap gates is self-timed so that no output exists until all necessary valid inputs are present.

REFERENCES:
patent: 4468575 (1984-08-01), Mathes
patent: 4569032 (1986-02-01), Lee
patent: 4570084 (1986-02-01), Griffin et al.
patent: 4682055 (1987-07-01), Upadhyayula
patent: 4692637 (1987-09-01), Shoji
patent: 4700086 (1987-10-01), Ling et al.
patent: 4730266 (1988-03-01), van Meerbergen et al.
patent: 4827160 (1989-05-01), Okano
patent: 4841174 (1989-06-01), Chung et al.
patent: 4899066 (1990-02-01), Aikawa et al.
patent: 5015882 (1991-05-01), Houston et al.
Weste and Eshraghian, Principles of CMOS VLSI Design, .sctn. 5.2.5-5.2.7, pp. 168-171.
Mead and Conway, Introduction to VLSI Systems, .sctn. 7.6-7.8.6, pp. 242-261.

Affiliated with

Also associated with

Rating

Functionally complete family of self-timed dynamic logic circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Functionally complete family of self-timed dynamic logic circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Functionally complete family of self-timed dynamic logic circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1977450