Functional register decoding system for multiple plane...

Details Functional register decoding system for multiple plane... Functional register decoding system for multiple plane...

2006-08-29

2006-08-29

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S189040

Reexamination Certificate

active

07099226

ABSTRACT:
A decoding system for multi-plane memories routes address information corresponding to distinct memory access operations to the designated planes. The system includes an array of functional registers dedicated to random access read, burst read, program, erase, and erase-suspend program operations. Plane selector blocks for each plane receive the address outputs from all of the registers and plane function select logic controls the routing in accord with memory access commands for specified planes. Simultaneous operations of different type in different planes and nested operations in the same plane are possible.

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