Functional MOS transistor with gate-level weighted sum and thres

Details Functional MOS transistor with gate-level weighted sum and thres Functional MOS transistor with gate-level weighted sum and thres

1994-05-24

1995-08-22

Wambach, Margaret Rose

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

Combining of plural signals

327408, 327566, 326 36, G06G 742, H03K 1762

Patent

active

054444110

ABSTRACT:
A threshold circuit that uses capacitors to form a weighted sum of its inputs uses a two stage capacitor structure. The two stages form a compact structure that increases the number of input signals that can be handled and increases the flexibility in assigning the weights to the input signals. Capacitor electrodes for the input signals are arranged in two sets and the electrodes of each set are electrostatically coupled to first and second electrodes. Third and fourth electrodes, which extend from the first and second electrodes respectively, are electrostatically coupled to a unitary structure of fifth and sixth electrodes where their voltages are summed. The fifth and sixth electrodes are conductively connected to the gate of an FET threshold circuit that responds to the weighted and summed input signals.

REFERENCES:
patent: 4734751 (1988-03-01), Hwang et al.
patent: 4988891 (1991-01-01), Moshiko
patent: 5028810 (1991-07-01), Castro et al.
patent: 5148514 (1992-09-01), Arima et al.
patent: 5293457 (1994-03-01), Arima et al.
patent: 5350953 (1994-09-01), Swenson et al.
Tadashi Shibata +Tadahiro Ohmi, in IEEE Transactions on Electron Devices, vol. 39, No. 6, Jun. 1992.

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