Boots – shoes – and leggings
Patent
1987-03-12
1989-04-25
Malzahn, David H.
Boots, shoes, and leggings
364757, G06F 752
Patent
active
048254010
ABSTRACT:
A multiplier array circuit including decoders for decoding a multiplier on the basis of Booth's algorithm; cell array blocks for receiving the selection signals from the decoders and a multiplicand and performing the multiplication of the multiplicand and the multiplier on the basis of Booth's algorithm; and an adder for obtaining the final products on the basis of the outputs from the cell array blocks. In order to enable the functionally divisional operation, the cell array blocks includes complex cells which operate as the basic cells in the non-division mode and which operate as the code cells in the division mode. Further, the cell array blocks include selectors to supply an inactive value to the cells to perform the multiplication of the upper bits of the multiplicand and the lower bits of the multiplier and to the cells to perform the multiplication of the lower bits of the multiplicand and the upper bits of the multiplier in such a manner that the cell array blocks can supply the multiplicand and its inverted data to the cells constituting the cell array blocks in the non-division mode and can simultaneously execute two series of multiplications in the division mode.
REFERENCES:
patent: 3814924 (1974-06-01), Tate
patent: 4122527 (1978-10-01), Swiatowiec
patent: 4153938 (1979-05-01), Ghest et al.
patent: 4575812 (1986-03-01), Kloker et al.
Patent Abstracts of Japan, vol. 10, No. 64 (P-436) [212], 14th Mar. 1986; & JP-A-60 205 746 (Toshiba K.K.) 17-10-1985.
D. A. Henlin et al., "A 24 MHz 16 Bit.times.16 Bit Pielined Multiplier," Proceedings IEEE International Conference on Computer Design, pp. 417-422, 1984.
Patent Abstracts of Japan, vol. 8, No. 286 (P-234) [1723], 27th Dec. 1984; & JP-A-59 149 540 (Toshiba K.K.) 27-08-1984.
Japanese Patent Disclosure (KOKAI) No. 60-205746 10/17/85.
Kabushiki Kaisha Toshiba
Malzahn David H.
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