Excavating
Patent
1979-12-12
1981-09-01
Atkinson, Charles E.
Excavating
324 73R, 371 20, 371 27, G01R 3128, G06F 1100
Patent
active
042875943
ABSTRACT:
Input test information and the expected value information stored in a main memory are stored in first and second local memories through first and second write circuits. The first and second local memories are addressed with given different phases by address control circuits, respectively, so that the first and second local memories produce the information in parallel fashion within given periods. The information outputted are temporarily stored into a data register which in turn applies it to the data multiplexer. Upon the application of the information, the data multiplexer converts the information inputted parallel thereto into serial information which in turn is applied to the input pattern format control circuit and a GO/NO GO judgment circuit. The response information from the integrated circuit to be tested is applied to the GO/NO GO judgment circuit where GO or NO GO of the integrated circuit is judged.
REFERENCES:
patent: 3651315 (1972-03-01), Collins
patent: 3961250 (1976-06-01), Snethen
patent: 3976940 (1976-08-01), Chau et al.
patent: 4168527 (1976-09-01), Winkler
patent: 4192451 (1980-03-01), Swerling et al.
patent: 4194113 (1980-03-01), Fulks et al.
Atkinson Charles E.
Tokyo Shibaura Denki Kabushiki Kaisha
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