Function generator for the production of a voltage across a node

Details Function generator for the production of a voltage across a node Function generator for the production of a voltage across a node

1977-06-02

1978-10-10

Anagnos, Larry N.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307238, 307246, 307262, 307279, 307DIG3, 365204, 365205, H03K 520, G11C 706, H03K 3353, H03K 3286

Patent

active

041198719

ABSTRACT:
A function generator is connected to a node formed by the source electrodes of the switching transistors of flip-flops in which the flip-flops are each composed of two circuit arms. Each of the circuit arms has a load transistor and a switching transistor, constructed as MOS transistors, for the amplification of read-out signals supplied by a MOS memory. Each flip-flop is connected at the connection points of the load transistors and switching transistors to a sub-portion of a bit line of the MOS memory. The curve of the voltage supplied to the node is such that, at the beginning of a cycle of the read-out process, the node is charged, and for the evaluation of the read-out signals on the bit lines the node is discharged in a controlled manner such that the flip-flops trigger into a state governed by the read-out signal on the bit lines. A pre-discharge circuit operates between the charging and discharging of the node to pre-discharge the node so that the switching transistors of the flip-flops connected to the node are rendered conductive, and the subportions of the bit lines are set at the voltage which prevails across the node, and which has been modified by the threshold voltage of the switching transistors of the flip-flops.

REFERENCES:
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patent: 3993917 (1976-11-01), Kalter
patent: 4000413 (1976-12-01), Wong et al.
patent: 4025907 (1977-05-01), Karp et al.
patent: 4027294 (1977-05-01), Meusberger et al.
patent: 4028557 (1977-06-01), Wilson
patent: 4050061 (1977-09-01), Kitagawa
Bishop et al., "High Sensitivity, High-Speed FET Sense Latch," IBM Tech. Discl. Bull.; vol. 18, No. 4, pp. 1021-1022; 9/1975.
Barsuhn et al., "Semiconductor Storage Circuit Utilizing Two Device Memory Cells," IBM Tech. Discl. Bull.; vol. 18, No. 3, pp. 786-787; 8/1975.
Stein et al., IEEE Journal of Solid-State Circuits, vol. SC-7, No. 5, pp. 336-340; 10/1972.

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