Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2005-07-29
2011-10-25
Gebremariam, Samuel (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257SE23060
Reexamination Certificate
active
08044511
ABSTRACT:
The semiconductor device is manufactured by forming a lower electrode layer2having a predetermined pattern on a semiconductor substrate1and forming an upper electrode layer3on a part of the top surface of the lower electrode layer2, while holes2X extending in the direction of thickness are formed on the top surface of the lower electrode layer2below the upper electrode layer3, and the depth of holes2X is smaller than the thickness of the lower electrode layer2.
REFERENCES:
patent: 6028011 (2000-02-01), Takase et al.
patent: 6462415 (2002-10-01), Ishiguri et al.
patent: 09069524 (1997-03-01), None
patent: 10130852 (1998-05-01), None
patent: 11-214421 (1999-08-01), None
patent: 2001196404 (2001-07-01), None
patent: 2002237497 (2002-08-01), None
patent: 2004172390 (2004-06-01), None
patent: 2004-200247 (2004-07-01), None
patent: 2004200247 (2004-07-01), None
Japanese language office action dated Sep. 21, 2010 and its partial English language translation for corresponding Japanese application 2006527874 lists the reference above.
Kato Ken-ichi
Shimoaka Yoshio
DLA Piper (LLP) US
Gebremariam Samuel
Kyocera Corporation
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