Function cell, semiconductor device including function cell,...

Details Function cell, semiconductor device including function cell,... Function cell, semiconductor device including function cell,...

1999-04-29

2002-07-09

Meier, Stephen D. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

C257S203000, C257S204000, C257S206000, C257S208000, C257S211000, C438S128000, C438S587000, C438S598000, C438S129000

Reexamination Certificate

active

06417529

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a function cell, a semiconductor device including the function cell, and a semiconductor circuit designing method using the function cell. More particularly, the present invention relates to a function cell used in cell-base semiconductor circuit designing, a semiconductor device including the function cell, and a semiconductor circuit designing method using the function cell.
2. Description of the Background Art
The semiconductor circuit designing method of the cell-base type, represented by the standard cell type, is conventionally known as one of the semiconductor circuit designing methods. In the cell-base type semiconductor circuit designing method, circuit designing of semiconductor devices has been carried out by combining function cells, according to users' demand, from a cell library that includes multiple kinds of function cells for realizing desired logic circuit functions.
FIGS. 11 and 12
are schematic plan views of function cells used in the conventional cell-base type semiconductor circuit designing method.
FIG. 13
is an equivalent circuit diagram showing the logic circuit function realized by the function cells shown in
FIGS. 11 and 12
. Referring to
FIGS. 11
to
13
, the function cells will be described.
Referring first to
FIG. 13
, an inverter is realized in the function cells shown in
FIGS. 11 and 12
. The inverter circuit includes two transistors
120
,
121
. Transistors
120
,
121
have their gate electrodes connected to an input terminal
112
. Here, p type field effect transistor
120
has its source region connected to an interconnection for a power supply (hereinafter, referred to as a power-supply interconnection)
110
and its drain region connected to the drain region of n type field effect transistor
121
and to an output pin terminal
106
a
. Further, n type field effect transistor
121
has its source region connected to an interconnection for a ground (hereinafter, referred to as a ground interconnection)
111
. The function cells shown in
FIGS. 11 and 12
are formed to realize such a logic circuit.
Referring to
FIG. 11
, the function cell includes p type impurity diffusion regions
107
a
,
107
b
, n type impurity diffusion regions
107
c
,
107
d
, gate electrodes
108
a
,
108
b
, input pin terminal
112
, output pin terminal
106
a
, power-supply interconnection
110
, and ground interconnection
111
. Impurity diffusion regions
107
a
to
107
d
are formed at a main surface of a semiconductor substrate. Between p type impurity diffusion regions
107
a
and
107
b
, gate electrode
108
a
is formed on the main surface of the semiconductor substrate with a gate insulation film (not shown) therebetween. Here, p type impurity diffusion regions
107
a
,
107
b
serving as source/drain regions, the gate insulation film, and gate electrode
108
a
constitute p type field effect transistor
120
.
In another region of the function cell, n type impurity diffusion regions
107
c
,
107
d
, the gate insulation film, and gate electrode
108
b
also constitute n type field effect transistor
121
. It is noted that n type field effect transistor
121
basically has a similar configuration to that of p type field effect transistor
120
.
On impurity diffusion regions
107
b
,
107
d
, output pin terminal
106
a
is formed with an interlayer insulation film (not shown) therebetween. Output pin terminal
106
a
and impurity diffusion region
107
b
are electrically connected via contact holes
109
g
,
109
h
. Output pin terminal
106
a
and n type impurity diffusion region
107
d
are electrically connected via contact holes
109
i
,
109
j.
On p type impurity diffusion region
107
a
, power-supply interconnection
110
is formed with an interlayer insulation film (not shown) therebetween. Power-supply interconnection
110
and p type impurity diffusion region
107
a
are electrically connected via contact holes
109
c
,
109
d
. On n type impurity diffusion region
107
c
, ground interconnection
111
is formed with an interlayer insulation film (not shown) therebetween. Ground interconnection
111
and n type impurity diffusion region
107
c
are electrically connected via contact holes
109
e
,
109
f
. On gate electrodes
108
a
,
108
b
, input pin terminal
112
is formed with an interlayer insulation film (not shown) therebetween. Gate electrode
108
a
and input pin terminal
112
are electrically connected via contact hole
109
a
. Gate electrode
108
b
and input pin terminal
112
are electrically connected via contact hole
109
b.
A longitudinal pin access route to input pin terminal
112
(route of an external interconnection to input pin terminal
112
) is denoted by
113
a
. Lateral pin access routes to input pin terminal
112
are denoted by
114
a
,
114
b
. A longitudinal pin access route to output pin terminal
106
a
is denoted by
113
b
. Lateral pin access routes to output pin terminal
106
a
are denoted by
115
a
to
115
f
. It is noted that the pin access route is a position in which a normally used route of an externally connected interconnection to input pin terminal
112
, output pin terminal
106
a
or the like of the function cell can be set during circuit designing.
The longitudinal length (height) and lateral length (width) of the function cell are set at H
7
and W
7
so that they become as small as possible in accordance with the sizes of field effect transistors
120
,
121
and the like.
FIG. 12
is a schematic plan view showing another function cell for realizing the logic circuit shown in
FIG. 13
, similarly to the function cell shown in FIG.
11
. Referring to
FIG. 12
, the function cell basically has a similar configuration to that of the function cell shown in FIG.
11
. In the function cell shown in
FIG. 12
, however, the size of impurity diffusion regions
107
e
to
107
h
is larger than that of impurity diffusion regions
107
a
to
107
d
. This is because, by changing the size of impurity diffusion regions
107
e
to
107
h
, the drivability of p type field effect transistor
120
and n type field effect transistor
121
is changed to realize electrical characteristics different from those of the function cell shown in FIG.
11
.
Since the configuration of p type field effect transistor
120
and n type field effect transistor
121
is changed to change the electrical characteristics as described above, the external shape (longitudinal length H
8
and lateral length W
8
, the external shape herein is determined by the longitudinal length and lateral length of a function cell) of the function cell shown in
FIG. 12
becomes larger than the external shape (longitudinal length H
7
and lateral length W
7
) of the function cell shown in FIG.
11
.
Since the external shape of the function cell is changed in this manner, the size and position of input pin terminal
112
and output pin terminal
106
b
in the function cell shown in
FIG. 12
are also changed as compared with the function cell shown in FIG.
11
. Accordingly, the position of longitudinal pin access route
113
c
in the function cell shown in
FIG. 12
is different from the position of longitudinal pin access route
113
a
in the function cell shown in FIG.
11
. Similarly, the position of lateral pin access routes
114
c
,
114
d
in the function cell shown in
FIG. 12
is also different from the position of lateral pin access routes
114
a
,
114
b
in the function cell shown in FIG.
11
.
Further, the position of longitudinal pin access route
113
d
and lateral pin access routes
115
g
to
115
n
to output pin terminal
106
b
in the function cell shown in
FIG. 12
is also different from the position of longitudinal pin access route
113
b
and lateral pin access routes
115
a
to
115
f
in the function cell shown in FIG.
11
.
FIG. 14
is a flow chart of a conventional cell-base type semiconductor device circuit designing process using the function cells shown in
FIGS. 11 and 12
. Referring to
FIG. 14
, the flow of the conventional sem

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