Function-based control interface for integrated circuit...

Data processing: measuring – calibrating – or testing – Testing system – Of circuit

Reexamination Certificate

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Details

C324S762010

Reexamination Certificate

active

06505138

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to integrated circuit (IC) testers and in particular to a function-based control interface for prober and handler devices that hold and position ICs for testing.
2. Description of Related Art
FIG. 1
illustrates a typical prior art system for testing one or more integrated circuits (IC) while still in the form of dies on a silicon wafer including a test head
1
, a prober
2
and a host computer
3
running a system control program
4
. Test head
1
contains circuits for generating test signal inputs to one or more IC dies on a wafer and for monitoring output signals produced by the dies in response to the test signals to determine whether the dies are behaving as expected. Prober
2
holds the wafer and positions the dies to contact the test head through probes while the dies are being tested. Host computer
3
communicates with both test head
1
and prober
2
to coordinate their activities. For example, host computer
3
communicates with prober
2
to determine when dies are in position and ready to be tested and then sends a START command to test head
1
to tell it to begin testing the dies. When test head
1
finishes the test, it returns the test results to host computer
3
.
Host computer
3
then typically tells prober
2
that the test is complete and that it may position a next set of dies on the same or another wafer for testing. Host computer
3
also provides prober
2
with information categorizing (“binning”) each die based on the test results for that die. Prober
2
maintains a record of that information for later use when the dies are being separated and packaged. Dies may be categorized in various ways depending on the nature of the tests being performed. For example when a die may be categorized simply as having passed or failed a test, the dies that pass the test may be separated from a wafer and packaged while dies that fail the test are discarded. When a test grades an IC dier for example according to its maximum operating frequency, the binning information may indicate how a packaged IC incorporating the IC die should be rated.
The host computer may also communicate with the prober to obtain information about the wafers being tested such as, for example, the nature of the ICs, the size of the wafer or the positions on the wafer of the particular dies currently under test. The host computer may use such information, for example, to determine how to program the test head or as input data for statistical reports regarding test failure rates of dies relative to their wafer positions.
IC testers can also test an IC after it has been packaged. In such case the prober, which handles wafers, is replaced with a “handler” for holding one or more packaged ICs as they are tested. The ICs are often mounted in an array on a “load board” the handler positions under the test head in a manner that is analogous to the way a prober positions a wafer containing several dies under a test head. Since many functions of probers and handlers are analogous, the host computer coordinates tester and handler activities in much the same way it coordinates tester and prober activities.
The many makes and models of test heads, probers and handlers produced by various manufacturers have differing sets of communication protocols and control requirements. Thus the system control program
4
that a host computer
3
executes when coordinating the activities of test head
1
and prober (or handler)
2
must be specifically adapted for the particular combination of test head and prober or handler the test system employs. The need to customize the system control program for each such combination adds to the difficulty and expense of mating a test head with any of several types of probers or handlers. What is needed is a way to avoid having to provide a customized system control program for each combination of test head and prober or handler.
SUMMARY OF THE INVENTION
An integrated circuit tester in accordance with the invention tests a set of integrated circuits (ICs) that may be implemented as dies in a group of wafers or as packaged ICs mounted on a load board. The tester includes a test head for testing the ICs and a prober or handler for holding each wafer or load board with one or more ICs in contact with the test head so that they may be tested. The test system also includes a host computer for coordinating activities of the test head and the prober or handler.
In accordance with one aspect of the invention, software executed by the host computer is partitioned into a device interface function library (DIFL)for directly communicating with the prober or handler and a test head control program (THCP) for directly communicating with the test head. In order to coordinate activities of the test head and the prober or handler, the THCP also indirectly communicates with the prober or handler by making function calls to the DIFL. With the DIFL being adapted to meet control and communication requirements of the specific prober or handler the system employs, the THCP can control and monitor prober or handler activities by making generic function calls that are independent of the nature of the prober or handler.
Accordingly a separate version of the DIFL may be prepared for each model of prober or handler, with each version responding to the same set of function calls in a manner appropriate to the control and communication requirements of the associated prober or handler model. Similarly a separate version of the test head control program may also be provided to suit the control and communication requirements of each model of test head with each version of the THCP making the same set of function calls to coordinate test head and prober or handler activities. This arrangement makes the test head control program for each variety of tests compatible without further adaptation with each variety of prober or handler.
It is accordingly an object of the invention to provide a software for a host computer that coordinates activities of an integrated circuit test head and a prober or handler.
It is another object of the invention to establish a system for facilitating software compatibility among varying models of test heads, probers and handlers.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.


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patent: 5329471 (1994-07-01), Swoboda et al.
patent: 5399983 (1995-03-01), Nagasawa
patent: 5644245 (1997-07-01), Saitoh et al.
patent: 5654588 (1997-08-01), Dasse et al.
patent: 5668470 (1997-09-01), Shelor
patent: 5834838 (1998-11-01), Anderson
patent: 5866024 (1999-02-01), de Villeneuve
patent: 6037793 (2000-03-01), Miyazawa et al.
patent: 6097204 (2000-08-01), Tanaka et al.
patent: 6111421 (2000-08-01), Takahashi et al.
patent: 6340895 (2002-01-01), Uher et al.

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