Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – With enlarged emitter area
Patent
1994-08-29
1997-03-25
Hille, Rolf
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
With enlarged emitter area
257586, 257587, H01L 27082, H01L 2943
Patent
active
056147589
ABSTRACT:
A self-aligned fully-walled monocrystalline silicon emitter-base structure for a bipolar transistor and methods for producing the structure are provided. The methods involve creating an oxide side wall surrounding a monocrystalline silicon emitter-base structure by first defining the emitter region in a base island region. Successive oxide layers are deposited on top of the emitter region and etched back to produce an oxide wall around the entire perimeter of the emitter region. In a preferred embodiment of the invention a metal silicide is also formed across the top of the base island region of the semiconductor outside of the emitter region. Since the extrinsic base region, outside of the oxide sidewalls, is entirely covered by a low resistance silicide film, the base contact area can be significantly reduced compared to prior art devices.
The process results in a fully-walled emitter-base structure made of monocrystalline silicon which exhibits improved high-frequency performance. The peripheral emitter-base capacitance is substantially decreased by the oxide walls which surround the emitter sides. Since the sides of the emitter are walled, no lateral current injection can occur. Bipolar transistors which employ the claimed process exhibit an increased emitter-base breakdown and a reduced forward tunneling current since high sidewall doping levels are eliminated.
REFERENCES:
patent: 3197681 (1965-07-01), Broussard
patent: 3586542 (1971-06-01), MacRae
patent: 3615939 (1971-10-01), Scneider
patent: 3826699 (1974-07-01), Sawazaki et al.
patent: 4012764 (1977-03-01), Satonaka
patent: 4195307 (1980-03-01), Jambotkar
patent: 4577212 (1986-03-01), Hueckel et al.
patent: 4698127 (1987-10-01), Hideshima et al.
patent: 4704786 (1987-11-01), Kub
patent: 4721685 (1988-01-01), Lindenfelser et al.
patent: 4812417 (1989-03-01), Hirao
patent: 4812894 (1989-03-01), Nakamura et al.
patent: 4824799 (1989-04-01), Komatsu
patent: 4847670 (1989-07-01), Monkowski et al.
patent: 4927775 (1990-05-01), Alvarez et al.
patent: 4967253 (1990-10-01), Jambotkar
patent: 4997775 (1991-03-01), Cook et al.
patent: 5198689 (1993-03-01), Fujioka
Solheim, et al., "Design and Optimization of Novel Transistor Structures", Ph.D. Thesis, Chapter 5, University of Wateloo, 1988.
El-Diwany, et al., "Increased Current Gain and Suppression of Peripheral Base Currents in Silicided Self-Aligned Narrow-Width Polysilicon-Emitter Transistors of an Advanced BiCMOS Technology", IEEE, Electron Device Letters, vol. 9, No. 5, pp. 247-249, May 1988.
De Jong, et al., "Electron Recombination at the Silicided Base Contact of an Advanced Self-Aligned Polysilicon Emitter", IEEE Proceedings, 1988, Bi-Polar Circuits and Tech. Meeting, pp. 202-205, Minneapolis, MN, Sep. 1988.
Van Es, et al., "PABLO vs. Double-Poly--A Comparison of Two High-Performance Bipolar Technologies".
Glenn, et al., "High-Speed Fully Self-Aligned Single-Crystal Contacted Silicon Bipolar Transistor", Electronics Letters, vol. 26, No. 20, Sep. 27, 1990.
Huang, et al., "A High-Speed Bipolar Technology Featuring Self-Aligned Single-Poly Base and Submicrometer Emitter Contacts", IEEE, Electron Device Letters, vol. 11, No. 9, Sep. 1990.
"Low-Noise Bipolars Silence Noise in 18-GHz YIG Source", Microwaves and RF, pp. 153-154, Nov. 1988.
D.J. Roulston, "Base Etched Self-Aligned Transistor Techology (BESTT)", Bipolar Semiconductor Devices, McGraw-Hill Publishing Co., pp. 351-353.
Konaka, et al., "A 30-ps Si Bipolar IC Using Super Self-Aligned Process Technology", IEEE Trans. Electron Devices, vol. ED-33, pp. 526-531, Apr. 1986.
Tang, et al., "Subnanosecond Self-Aligned I.sup.2 L/MTL Circuits", IEEE Trans. Electron Devices, vol. ED-28, pp. 1370-1384, Aug. 1980.
Wolstenholme, et al., "An Invest. of the Thermal Stability of the Inter. Oxide in Polycrystalline Silicon Emitter Bipolar Trans. by Comparing Dev. Results with High-Resolution Electron Microscopy Ob.", J. Appl. Physics, vol. 61, pp. 225-233, Jan. 1, 1987.
E.H. Stevens, "Consequence of Contact Resistance in Very-Small-Geometry CML Gates", Microelectronics Journal, vol. 14, No. 5, pp. 15-20, 1983.
Chuang, et al., "On the Narrow-Emitter Effect of Advanced Shallow-Profile Bipolar Transistors".
Chantre, et al., "An Investigation of Nonideal Base Currents in Advanced Self-Aligned Etched-Polysilicon Emitter Bipolar Transistors", IEEE Transactions on Electron Devices, vol. 38, No. 6, pp. 1354-1361.
Fahmy Wael M.
Hewlett--Packard Company
Hille Rolf
LandOfFree
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