Fully synchronous pipelined ram

Details Fully synchronous pipelined ram Fully synchronous pipelined ram

1997-05-28

1999-02-23

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Sync/clocking

365191, 3652335, G06F 1300

Patent

active

058751513

ABSTRACT:
A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no "bus turnaround" down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

REFERENCES:
patent: 5515325 (1996-05-01), Wada
patent: 5526320 (1996-06-01), Zagar et al.
patent: 5546344 (1996-08-01), Fawcett
patent: 5568430 (1996-10-01), Ting
patent: 5577236 (1996-11-01), Johnson et al.
patent: 5617362 (1997-04-01), Mori et al.
patent: 5652724 (1997-07-01), Manning
patent: 5675549 (1997-10-01), Ong et al.
patent: 5699317 (1997-12-01), Sartore et al.

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