Fully static 32 bit alu with two stage carry bypass

Details Fully static 32 bit alu with two stage carry bypass Fully static 32 bit alu with two stage carry bypass

1994-03-01

1995-08-22

Mai, Tan V.

Boots, shoes, and leggings

364786, G06F 700, G06F 750

Patent

active

054446465

ABSTRACT:
A multiply/accumulate unit utilizes a fully static 32-bit arithmetic logic unit with two stage carry bypass. A four transistor carry chain places minimal loading on the chain.

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patent: 5146424 (1992-09-01), Peterson et al.
Ferro, et al. "The Architecture and Programming of the WE.RTM. DSP16 Digital Signal Processor", Electro/87 and Mini/Micro Northeast Conference Record, vol. 12, 1987, Los Angeles, Calif., USA; paper 27/4; pp. 1-7.
Ware, et al. "64 Bit Monolithic Floating Point Processors", IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, Oct. 1982, New York, USA; pp. 898-907.

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