Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – With non-planar semiconductor surface
Reexamination Certificate
2001-12-03
2003-01-14
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
With non-planar semiconductor surface
C438S343000
Reexamination Certificate
active
06507090
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of an Electro Static Discharge (ESD) device and more particularly an Electro Static Discharge (ESD) device using a silicide process. The invention related to a device for on-chip ESD protection.
2) Description of the Prior Art
The n-type MOS transistor has been widely employed as the primary component for an ESD protection circuit in semiconductor IC devices. It is well known that silicidation of the drain and LDD junctions reduce ESD performance significantly. Most salicided process have a removal option which allows unsalicided areas (e.g., resistors) to be formed and use ESD implant to make junction deeper and to overdose the lightly doped region of the LDD for better ESD performance.
NMOS transistors stacked in a cascade configuration provide robust ESD protection for mixed voltage I/O in both silicided and silicide-blocked technologies. However, this kind of device has high snapback voltage. Also, the high snapback voltage of the stacked NMOS degrades its IT
2
(IT
2
is the second breakdown trigger current)) since the power dissipation is great. The IT
2
is the current at or before the MOS gets into secondary breakdown (thermal/permanent damages) The higher the It
2
, the more robust the NMOS and the higher the ESD threshold. For the process technology where the silicide block and abrupt junction steps were are not available, a biasing network was necessary to ensure uniform triggering of all fingers. So, the need for high voltage tolerant I/O's severely complicates ESD protection.
FIG. 5A
shows a single poly N-MOS device that is used in the prior art as an ESD device. The structure and snap back mechanism are described below. The single-poly N-MOS device is shown in cross section and layout in FIG.
5
A.
FIG. 5B
shows a top plan view.
FIG. 5C
shows the IV curve and snap back curve for the ESD device. Vsp is the snapback holding voltage.
FIG. 5D
shows the electrical schematic of the device in FIG.
5
A. When a short-duration (100 to 110 ns) constant current pulse is applied to the drain with the source and gate tied to the substrate (substrate grounded), the device should have the I-V characteristic shown in FIG.
5
C. At normal operation, the device is off because the gate is grounded. When the drain breakdown voltage, BVdss is reached, current starts to flow as a result of impact ionization of die reverse-biased drain junction. At current It
1
, and voltage Vt
1
, the device triggers into snapback. The trigger current It
1
and voltage is related to the channel length and BVdss. Note that the trigger point (Vt
1
, It
1
,) is not the same as BVdss. BVdss, usually is defined as the drain junction avalanche breakdown voltage at a specified drain current density. The trigger point is the point that has the highest voltage just before snapback. The snapback region of the I-V curve is roughly linear and, therefore, may be represented by a snapback voltage Vsb and a differential resistance Rsb. The snapback voltage Vsb is defined as the linear extrapolation of the snapback region back to zero current. Care must be taken to avoid defining Vb and Rb by extrapolating from low current values near the point where the I-V curve changes slope from negative to positive. Therefore, the values of Vsb and Rsb were obtained from measurements made at high currents with the transmission-line pulse technique. Because the high-current values are relevant to ESD events, we need to use them rather than the low-current values when designing for protection against ESD. With sufficiently high current It
2
, flowing in the snapback region, the device triggers into second breakdown. We define a second trigger point (Vt
2
, It
2
) corresponding to the triggering from snapback into second breakdown. Second breakdown is the term used for power bipolar devices to indicate the regime of thermal runaway and current-instability.
The following patents show related ESD devices: U.S. Pat. No. 5,898,205(Lee), U.S. Pat. No. 5,519,242(Avery), U.S. Pat. No. 5,969,923(Avery), U.S. Pat. No. 5,559,352(Hsue et al.), U.S. Pat. No. 5,043,782(Avery) and U.S. Pat. No. 5,689,113(Li et al.).
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a structure of an Electro Static Discharge (ESD) device that provides better protection without process changes and additional costs.
It is an object of the present invention to provide an IC design having a structure of an Electro Static Discharge (ESD) device to be used in IC chip manufactured with a silicided process.
It is an object of the present invention to provide a method and a structure of an ESD device that overcomes the problems associated with silicided drains.
It is an object of the present invention to provide a method and a structure of an ESD device for a silicided process that does not add any extra processes steps or cost.
To accomplish the above objectives, the present invention provides a method and a structure of for an Electro Static Discharge (ESD) device that is silicided. There are three preferred embodiments of the invention.
The first embodiment has a butted N/P/N structure. The emitter, the collector and the substrate form a parasitic transistor and the substrate is connected to the p+ diffusion region. The emitter and the substrate act as a first diode D
1
. The collector and the substrate act as a second diode D
2
. The butted NPN structure is important because it ensures that the first triggering voltage sufficiently lower than the gate oxide breakdown.
The second embodiment has a first N+ well between a second N+ (collector) region and a P+ base region. The Vt
1
is controlled by the dopant profiles of the P+ base and the n− first well where they intersect.
The third embodiment is similar to the second embodiment, but the n− well covers all of drain. A parasitic NPN bipolar transistor comprises an emitter, a parasitic base and a drain. The emitter formed by the first n+ region. The parasitic base formed by the p-substrate. The collector formed by the second n+ region and the first n− well. The Vt
1
is controlled by the dopant profiles of the P+ base and the n− first well where they intersect.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 5043782 (1991-08-01), Avery
patent: 5103281 (1992-04-01), Holloway
patent: 5519242 (1996-05-01), Avery
patent: 5559352 (1996-09-01), Hsue et al.
patent: 5602404 (1997-02-01), Chen et al.
patent: 5689133 (1997-11-01), Li et al.
patent: 5898205 (1999-04-01), Lee
patent: 5969923 (1999-10-01), Avery
patent: 6268639 (2001-07-01), Li et al.
patent: 6281554 (2001-08-01), Pan
patent: 6348724 (2002-02-01), Koomen et al.
patent: 406232393 (1994-08-01), None
Chen et al., “Design Methodology and Optimizaion of Gate-Driven NMOS ESD Protection Circuits in Submicron CMOS Processes,” IEEE Trans. on Electron Devices, vol. 45, No. 12, Dec. 1998, pp. 2448-2456.
Amerasekera et al., “Correlating Drain Junction Scaling, Salicide Thickness, and Lateral NPN Behavior, with the ESD/EOS Performance of a 0.25 um CMOS Process”, 1996 IEEE, IEDM 96-893 to 96-896.
Polgreen et al., “Improving the ESD Failure Threshold of Silicided n-MOS Output Transistors by Ensuring Uniform Current Flow,” IEEE Trans. on Electron Devices, vol. 39, No. 2, Feb. 1992, pp. 379-388.
Notermans et al., “The Effect of Silicide on ESD Performance,” IEEE 1999, 37th Annual International Reliability Physics Symposium, San Diego, CA, pp. 154-158.
Charvaka Duvvury, “ESD: Design for IC Chip Quality and Reliability” 2000 IEEE, pp. 251-259.
Cai Jun
Hu David
Chaudhuri Olik
Farahani Dana
Nano Silicon Pte. Ltd.
Stoffel William J.
LandOfFree
Fully silicide cascaded linked electrostatic discharge... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fully silicide cascaded linked electrostatic discharge..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fully silicide cascaded linked electrostatic discharge... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3027484