Fully scan-set testable embedded edge-triggered dual D and J-K f

Details Fully scan-set testable embedded edge-triggered dual D and J-K f Fully scan-set testable embedded edge-triggered dual D and J-K f

1983-06-13

1986-05-13

Levy, Stewart J.

Electricity: measuring and testing

Plural, automatically sequential tests

371 25, G01R 3128, H03K 1900

Patent

active

045889449

ABSTRACT:
Additional logical structures are respectively interactive with either an edge-triggered dual D-type flip-flop or an edge-triggered J-K flip-flop in order that each such flip-flop may be fully scan-set testable in all the elements thereof. Two scan-set test enabling signals, as well as two scan-set clock signal, are used to conduct three tests, as well as enabling normal edge-triggered operation. The three tests enable scan-set testability of the totality of the edge-triggered flip-flop. Two of the tests characteristically cause the logical interconnection of tested logical elements as inverter strings, which inverter strings are merged into the scan-set test loops. In addition to supporting functional logical verification, the inverter strings support the evaluation of propagation time upon such strings in order to determine the operational speed and/or impedance environment of the tested flip-flops. Marginal, as well as failed, flip-flops (flip-flop environments) are identifiable.

REFERENCES:
Bodner, R., "100% Testable D-Type Flip-Flop", IBM Technical Disclosure Bulletin, vol. 15, No. 8, Jan. 1973, pp. 2487-2488.
Finlay, D., "Latch Circuit Operable as a D-Type Edge Trigger", IBM Technical Disclosure Bulletin, vol. 22, No. 12, May 1980, pp. 5261-5262.
McCluskey, E., "Built-In Self Test Structures", IEE Design & Test, Apr. 1985, pp. 29-36.
Stewart, J., "Future Testing of Large LSI Circuit Cards", Digest 1977 Semiconductor Test Symp., Cherry Hill, N.J., Oct. 1977, pp. 6-15.
Stewart, J., "Application of Scan/Set for Error Detection and Diagnostics", Digest 1978 Semiconductor Test Conf., Cherry Hill, N.J., Oct. 1978, pp. 152-158.

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