Fully scalable memory apparatus

Details Fully scalable memory apparatus Fully scalable memory apparatus

1993-10-04

1994-10-11

Fears, Terrell W.

Static information storage and retrieval

Addressing

36523003, 36523008, 365200, G11C 1300

Patent

active

053553454

ABSTRACT:
A memory is partitioned into rows and columns of memory blocks comprised of latches, sense amplifiers, and logic circuitry that form independent pipelines through which flow a) input addresses for memory access requests and b) data to be written into a specific memory cell within a memory block. The memory allows multiple data access requests in consecutive clock cycles to be pipelined in the rows and columns of memory blocks such that the memory clock speed is equal to the clock speed of a single memory block, independently of the memory size.

REFERENCES:
patent: 5199033 (1993-03-01), McGeoch et al.
T. Hirose, H. Kuriyama, S. Murakami, K. Yuzuriha, T. Mukai, K. Tsutsumi, Y. Nishimura, Y. Kohn, K. Anami, "A 20-ns 4-Mb CMOS SRAM with Hierachical Word Decoding Architecture", IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct., 1990.
S. Aizaki, T. Shimizu, M. Ohkawa, K. Abe, A. Aizaki, M. Ando, O. Kudoh, I. Sasaki, "A 15ns 4-Mb CMOS SRAM", IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct., 1990.
T. I. Chappel, B. A. Chappel, S. E. Schuster, J. W. Allan, S. P. Klepner, R. V. Joshi, R. L. Franch, "A 2-ns Cycle, 3.8-ns Access 512-kb CMOS ECL SRAM with a Fully Pipelined Architecture", IEEE Journal of Solid-State Circuits, vol. 26, No. 11, Nov., 1991.
D. Schmitt-Landsiecel, B. Hoppe, G. Neuendorf, W. Wurm, J. Winnerl, "Pipeline Architecture for Fast CMOS Buffer RAM's", IEEE Journal of Solid-State Circuits, vol. 25, No. 3, Jun., 1990.
J. Yuan, C. Svensson, "High-Speed CMOS Circuit Technique", IEEE Journal of Solid-State Circuits, vol. 24, No. 1, Feb., 1989.
D. W. Dobberpuhl e4t al., "A 200Mhz 64-b Dual-Issue CMOS Microprocessor", IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov., 1992.

Affiliated with

Also associated with

Rating

Fully scalable memory apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fully scalable memory apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fully scalable memory apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1664343