Fully programmable multimodulus prescaler

Details Fully programmable multimodulus prescaler Fully programmable multimodulus prescaler

2001-06-07

2002-12-31

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

C377S052000, C377S116000, C327S115000, C327S117000

Reexamination Certificate

active

06501816

ABSTRACT:

BACKGROUND
FIELD OF THE INVENTION
This invention relates to digital circuits. In particular, the invention relates to pre-scaler.
BACKGROUND OF THE INVENTION
Pre-scaler circuits are useful in many applications such as clock generation in digital circuits and phase-locked loop (PLL) circuits. It is usually desired to divide a clock signal by an integer N.
Existing techniques to provide divide-by-N uses a series of divide by ⅔ sections. These techniques are limited to division ratios between 2
k
and 2
k
+1−1, where k is the number of the 2-3 cells in cascade. These techniques therefore cannot be used for division ratios beyond the bands of 2
k
and 2
k
+1−1. In addition, the reloading of these circuits is done asynchronously by a separate strobe signal. The asynchronous reloading typically leads to additional hardware, added power consumption and high noise.


REFERENCES:
patent: 5339345 (1994-08-01), Mote, Jr.
Michael H. Perrott et al., “A 27-mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2/5-Mb/s GFSK Modulation”, IEEE Journal of Solid-State Circuits, vol. 32, No.12, pp. 2048-2060, Dec. 1997.
Cicero Vaucher et al., “A Wide-Band Tuning System for Fully Integrated Satellite Receivers”, IEEE Journal of Solid-State Circuits, vol. 33, No. 7, pp. 987-997, Jul. 1998.

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