Fully planar metalization process

Details Fully planar metalization process Fully planar metalization process

1991-10-10

1993-02-02

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 24, 437187, 437195, 437245, 148DIG50, 427437, 427304, 427305, H04L 2102

Patent

active

051837951

ABSTRACT:
A planar interconnect using selective, electroless deposition of a metal such as copper into interconnect channels is disclosed. A first dielectric layer is deposited on the surface of a substrate, such as an integrated circuit wafer. Thereafter, a second dielectric layer is formed on the first dielectric layer. Then a photoresist layer is spun on the top surface of the second dielectric layer. Channels are formed in the dielectric layers by patterning and etching the composite dielectric layers. Silicon atoms are implanted in the bottom of the interconnect channels and then the metal layer is selectively, electrolessly deposited to fill the channels in the first dielectric film, thus forming a level of interconnect. This process is repeated to form subsequent levels of interconnect.

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