Fully pipelined and highly concurrent memory controller

Details Fully pipelined and highly concurrent memory controller Fully pipelined and highly concurrent memory controller

1993-03-22

1996-07-16

Harvey, Jack B.

395280, 395285, 395308, 395309, 395310, 395311, G06F 1300

Patent

active

055375553

ABSTRACT:
A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine completes its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.

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Texas Instruments, TACT84500 EISA Chip Set User's Guide, Oct. 10, 1991 preliminary.

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