Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-02-03
2001-07-10
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S307000, C257S535000
Reexamination Certificate
active
06259149
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to trench capacitors, and particularly to a process for forming a fully isolated thin-film trench capacitor and trench capacitors made thereby.
Custom analog integrated circuits require use of capacitors for AC coupling, noise bypassing, supply filtering, etc. While discrete capacitors have been used for such purposes, there has been increased interest in integrating these capacitors onto chips with other circuitry. Integration of capacitors onto chips is commonly performed for DRAM cells where capacitors and MOSFET devices form bit cells for storing data. There are several advantages associated with the inclusion of capacitors on chips, including reduced parasitic inductance, and simpler assembly at the circuit board level. However, some analog functions require the integration of a few (10 to 20) capacitors in the hundreds'picofarad range, resulting in 2 or 3 nanofarads of capacitance for each chip, whereas a 1 gigabit DRAM chip will contain about 10° capacitors each having about 35 femtofarads, resulting in about 35 microfarads of capacitance per chip. While the total capacitance of the DRAM chip may be greater than the analog chip, the capacitance of individual capacitors on the analog chip is greater than on the DRAM chip.
Stray (parasitic) capacitance is a factor in the successful operation of electronic chips. Total chip capacitance and individual capacitance on the chip are independent factors affecting parasitic capacitance on a chip. Also, operating voltages of the chip, dielectric materials, chip layout and geometry, and chip processing are all factors affecting parasitic capacitances in the chip and the operation of the chip.
There are three basic families of on-chip capacitors: planar, stack, and trench. A planar capacitor is one in which the plates and dielectric material are positioned in single planes to form a generally two-dimensional, planar capacitor on a surface of the chip. Planar capacitors ordinarily take up a considerable amount of real estate on a chip, and suffer from limitations in terms of capacitance density, linearity and parasitic capacitance. Stack and trench capacitors are more threedimensional in shape, either interleaving the capacitive plates to form a stack of interleaved plates, or extending the capacitive plates in directions both normal and parallel to the plane of the chip, or both. Stack capacitors extend above the topography of the chip, and are usually constructed in the later stages of fabrication of the chip. Trench capacitors, on the other hand, extend into the chip and below the circuitry of the chip, thereby resulting in a planar topography of the chip. Both stack and trench capacitors offer the advantage of increased capacitance density. However, the choices for dielectric material are more limited in trench capacitors than in stack capacitors because the trench capacitor is usually fabricated early in the fabrication process and the dielectric material must be reasonably thermally stable to withstand subsequent chip fabrication processing. Thus, stack capacitors offer the advantage of a wider choice of dielectric material because they are fabricated late in the process. While stack capacitors offer a greater range of materials in fabrication, they are more severely limited in placement on the chip, and the raised topography of stack capacitor cause depth-of-focus problems that increase the difficulty of subsequent process integration. Trench capacitors, although more limited in material choices, may be fabricated in more convenient locations on the chip, and provide a planar topography to the chip that does not interfere with subsequent processing.
While trench capacitors are often used in DRAM cells as the storage capacitor that operates with a MOSFET transfer device, they are not altogether suitable for analog applications. More particularly, trench capacitors in DRAM cells are typically operated at 1-2 volts, whereas integrated on-chip capacitors in analog circuits are typically operated at about 8 volts, although operating voltages in excess of 12 volts are not unusual. Moreover, the individual trench capacitors of a DRAM chip are typically about 35 fF, whereas capacitors on a typical analog chip are typically in the hundreds of picofarads capacity. Analog circuits are more sensitive to parasitic capacitances than DRAM circuits, and require capacitors that are more insensitive to applied voltages than trench capacitors in DRAM circuits. There is a need for a trench capacitor useful for analog applications.
BRIEF SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a process is provided for forming an isolated thin-film trench capacitor. A first trench is formed in a substrate and filled with an electrically insulating material. A trench capacitor is formed in the first trench by forming first and second pluralities of conductive plates, such as polycrystalline silicon, separated by a layer of dielectric material. The first plurality of conductive plates are electrically connected together and the second plurality of conductive plates are electrically connected together.
In one form of this aspect of the invention, a plurality of second trenches are formed in the electrically insulating material spaced from each other. The first plurality of conductive plates are formed by depositing conductive material onto exposed surfaces of the electrically insulating material to thereby form a continuous first conductive layer in the second trenches and on the exposed surface of the electrically insulating material between the second trenches. The first conductive layer is deposited to a thickness as to only partially fill the second trenches. The layer of dielectric material is formed on the exposed surface of the first conductive layer to a thickness as to only partially fill the second trenches. The second plurality of conductive plates are formed by depositing conductive material onto exposed surfaces of the dielectric layer to thereby form a continuous second conductive layer in the second trenches and on the exposed surface of the electrically insulating material between the second trenches. The second conductive layer is deposited to a thickness as to substantially fill the second trenches.
In another form of this aspect of the invention, a second trench is formed in the electrically insulating material. The trench capacitor is formed by depositing a first layer of conductive material onto exposed surfaces of the electrically insulating material in the second trench. The first layer of conductive material is patterned to expose a portion of the electrically insulating material at the bottom of the second trench adjacent a first side of the second trench, thereby separating the first conductive layer into first and second side portions with the portion at the bottom being electrically connected to the second side portion. A first dielectric layer is formed on the bottom portion of the first conductive layer and the exposed portion of the electrically insulating material. A second layer of conductive material is formed on the first dielectric layer exposed surfaces of the electrically insulating material in the second trench, the second conductive layer electrically engaging the first side portion of the first conductive layer and being spaced from the second side portion of the first conductive layer to expose a portion of the first dielectric layer. A second dielectric layer is formed on the second conductive layer and the exposed portion of the first dielectric layer.
A desirable feature of this aspect of the invention resides in a third layer of conductive material is patterned on the second dielectric layer, the third conductive layer electrically engaging the second side portion of the first conductive layer and being spaced from the first side portion of the first conductive layer to expose a portion of the second dielectric layer. A third dielectric layer is formed on the third conductive layer and the exposed portion of the second dielec
Burkhardt Joseph J.
Fertig Daniel J.
Schweigert Jeremy A.
Agere Systems Guardian Corp.
Kinney & Lange , P.A.
Meier Stephen D.
Vockrodt Jeff
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