Fully integrated cache architecture

Details Fully integrated cache architecture Fully integrated cache architecture

1995-06-07

1998-02-10

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365 51, 365 63, G11C 700

Patent

active

057176485

ABSTRACT:
An integrated cache architecture that has low power consumption, high noise immunity, and full support of an integrated validity/LRU cache write mode. The cache stores TAG, index and LRU information directly on a master word line, and cache line data on local word lines. The access information is made available early in the cycle, allowing the cache to disable local word lines that are not needed. By laying out the master and local word lines in a metal layer that substantially renders the stored data immune to overlaying noise sources, high frequency interconnections can be made over the cache without disturbing the stored data. The cache includes circuitry for efficiently updating the stored LRU information, such that a combined data validity/full LRU cache update protocol is supported.

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