Fully integrated architecture for improved sigma-delta...

Pulse or digital communications – Receivers – Automatic gain control

Reexamination Certificate

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Details

C375S346000, C341S143000, C341S172000

Reexamination Certificate

active

06278750

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the circuit design of a (&Sgr;-&Dgr;) modulator and an automatic gain controller (AGC) implemented as integrated circuits(ICs) on a semiconductor chip. More particularly, this invention relates to an improved circuit design and architecture to more completely integrate a (&Sgr;-&Dgr;) modulator with an automatic gain controller (AGC) circuit such that areas occupied by the circuits on a semiconductor chip are reduced and better signal to noise ratio are achieved when less signal distortions are generated by implementing the improved circuit design disclosed by this invention.
2. Description of the Prior Art
A circuit designer is faced with the difficulties that wastes of wafer areas on a semiconductor chip and a great deal of signal distortions are often resulted from applying a conventional circuit design architecture for implementing an automatic gain controller (AGC) and a sigma-delta modulator in an integrated circuit (IC) chip. Specifically, the automatic gain controller and the sigma-delta modulator are designed separately as two independent circuit elements. A multiplexer is then employed for interconnecting these two independent separate circuit elements for processing an output signals from the automatic gain controller (AGC) to generate an input signal to the sigma-delta modulator.
FIGS. 1
shows a functional block diagram of a conventional circuit implementation of an automatic gain controller (AGC) and a sigma-delta (&Sgr;-&Dgr;) modulator. This conventional circuit implementation employs a dual-path architecture where the input signal is transmitted via a first path, i.e., path-A, to be first processed by a gain controller (AGC). The input signal is also transmitted via a second path, i.e., path-B, as a direct input signal. An output generated by the gain controller AGC and the direct input signal via the second path path-B are inputted to a multiplexer (MUX) and a signal is selected between two signals as an input to a sigma-delta (&Sgr;-&Dgr;) modulator to complete the analog to digital conversion. As will be further explained below there are several difficulties and limitations imposed by this dual path configuration.
FIG. 2
shows a functional block of the automatic gain controller AGC of FIG.
1
. The input signal to the AGC is first processed by a variable gain amplifier (VGA) and the output therefrom is then further processed by a gain amplifier A to generate an AGC output signal. The output signal is further inputted to a feedback loop which includes a high pass filter, a full wave rectifier and a peak detector to produce a feedback signal for inputting to the variable gain amplifier VGA to adjust the value of the gain such that the output of VGA is adjusted to have a fixed peak value. One definite disadvantage of this type of signal processing scheme is the reduction of the signal to noise ratio (SNR) when the amplitude of the input signal is increased. The reasons that the SNR is reduced with the increase of input signal will be further explained below when a comparison is made with the variations of the SNRs produced by a signal processing circuit of this invention.
Therefore, a need still exists in the art of circuit design and integrated circuit manufacture to provide a novel circuit design architecture to resolve the above difficulties. It is desirable that the circuit configuration can be conveniently implemented on a semiconductor chip as integrated circuited occupying less chip areas. It is further desirable that improved sigma-delta modulator can achieve better signal to noise ratios such that signal distortions produced can be significantly reduced.
SUMMARY OF THE PRESENT INVENTION
It is therefore an object of the present invention to provide a novel and improved circuit configuration and architecture for more fully integrating the AGC and the sigma-delta modulator to reduce the area requirements on a semiconductor chip and to improve the signal to noise ratio such that the aforementioned difficulties and limitations encountered in the prior art can be overcome.
Specifically, it is an object of the present invention to provide a novel and improved circuit design architecture and configuration of circuit implementation to perform more fully integrated AGC and sigma-delta modulation functions such that the areas occupied by these circuits on a semiconductor chip can be reduced.
Another object of the present invention is to provide a novel and improved circuit design architecture and configuration of circuit implementation to perform more fully integrated AGC and sigma-delta modulation functions such that the signal to noise ratios are improved with less signal distortions generated from the improved signal processing device.
Another object of the present invention is to provide a novel and improved circuit design architecture and configuration of circuit implementation to perform more fully integrated AGC and sigma-delta modulation functions such that better AGC performance is obtained by achieving improved of input/output transfer function.
Briefly, in a preferred embodiment, the present invention discloses an automatic gain control (AGC) feedback-referenced sigma-delta modulating device provided for processing an analog signal received therein. This device includes an automatic gain controller (AGC) for receiving processing the analog input signal for generating an AGC feedback including a set of positive and negative AGC reference voltages. This device further include a sigma-delta modulator for receiving the analog input signal and the AGC feedback of the set of the positive and negative AGC reference voltages for generating a one binary bit output therefrom. In a preferred embodiment, the automatic gain controller (AGC) includes a peak detector for receiving and detecting a peak input voltage of the analog input signal. The automatic gain controller (AGC) further includes a maximum gain control block for receiving the peak input voltage from the peak value detector for generating a maximum gain controlled peak value Vp. And, the automatic gain controller (AGC) further includes a positive-and-negative AGC reference voltage (Vref
+_
AGC, Vref
−_
AGC) generation block for receiving and applying the maximum gain controlled peak value Vp to generate a positive AGC reference voltage Vref+_AGC and a negative AGC reference voltage Vref
−_AGC.
The present invention further discloses a method for generating an automatic gain control (AGC) feedback-referenced sigma-delta modulating signal from an analog input signal. The method includes the step of a) an automatic gain controller (AGC) for receiving processing the analog input signal for generating an AGC feedback including a set of positive and negative AGC reference voltages; and b) applying a sigma-delta modulator for receiving the analog input signal and the AGC feedback of the set of the positive and negative AGC reference voltages for generating a one binary bit output therefrom. In a preferred embodiment, the step a) of applying the automatic gain controller (AGC) for generating an AGC feedback further includes a step a
1
) of applying a peak detector for receiving and detecting a peak input voltage of the analog input signal; a
2
) applying a maximum gain control block for receiving the peak input voltage from the peak value detector for generating a maximum gain controlled peak value Vp; and c) applying a positive-and-negative AGC reference voltage (Vref
+_AGC, Vref
−_AGC) generation block for receiving and applying the maximum gain controlled peak value Vp to generate a positive AGC reference voltage Vref
+_AGC and a negative AGC reference voltage Vref
−_AGC.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various drawing figures.


REFERENCES:
patent: 5084702 (1992-01-0

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