Fully-hidden refresh dynamic random access memory

Details Fully-hidden refresh dynamic random access memory Fully-hidden refresh dynamic random access memory

2006-12-05

2006-12-05

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S222000, C365S240000

Reexamination Certificate

active

07145832

ABSTRACT:
A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.

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