Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
1999-12-02
2001-10-16
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S760000, C257S702000, C257S701000, C257S758000, C257S723000, C257S620000, C257S644000, C257S788000, C257S791000, C257S792000, C257S784000, C257S786000
Reexamination Certificate
active
06303977
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related in general to the field of semiconductor devices and processes, and more specifically to a method for fabricating hermetic semiconductor chips.
DESCRIPTION OF THE RELATED ART
More than two decades ago, a process was developed to deposit a continuous layer of silicon nitride over the whole surface of a semiconductor wafer having a multitude of integrated circuit fabricated in it. Silicon nitride is not penetrated by water molecules (in contrast to silicon dioxide previously used as layer material), so that whenever a layer of silicon nitride is fabricated free of pinholes, it should protect the integrated circuits against moisture.
Following the silicon nitride layer deposition, however, the uniformity of this layer has to be interrupted by two unavoidable process steps: First, windows have to be etched through the overcoat to expose the metallization of the contact pads in order to enable wire bonding during the assembly process; consequently, this metallization, conventionally aluminum or copper, is exposed to potential degradation by moisture (corrosion). Second, the overcoat has to be cut apart in the sawing process which singulates the chips from the wafer; consequently, the edge sides of the chips are exposed and remain unprotected against potential penetration by moisture.
In order to operate semiconductor chips reliably in a moisture-proof environment, they are conventionally assembled in a package made of ceramic material, which is impermeable to moisture. Unfortunately, these hermetic packages are considerably more expensive than commercial plastic molded packages, which allow water molecules to penetrate through the plastic material (in standard pressure cooker testing, the first water molecules reach the chip inside after about 1 hour). Consequently, significant effort has been directed in the last few years to develop methods of protecting the contact pad aluminum after wire bonding or solder bumping so that the chips would be “hermetic” even in a plastic package. Particularly noteworthy is the “ChipSeal™ Process” by the Dow Corning Corporation, Midland, Mich., USA; see for example M. J. Loboda, “Safe Processes for Hard Dielectric Coatings: Growth of Silicon-Carbon Alloy Films from Organosilicon Gases”, Proc. 124th Minerals, Metals & Materials Soc. (TMS) Ann. Meet., pp. 281-290, 1995; M. J. Loboda et al., “Chip Scale Packaging with High Reliability for MCM Applications”, Intl. J. Microcircuits and El. Packaging, pp. 428-433, 1997. In this technology, silicon carbon alloy thin films are deposited by chemical vapor deposition techniques using gas mixtures of SiH4 and hydrocarbons, or alternatively organosilicon molecules. Properly engineered SiC films offer hermetic-like performance when used to protect surfaces from mechanical abrasion and corrosion. This technology has been successfully applied to protect bonding pads in silicon BiCMOS devices.
An alternative, metallurgical method of protecting the aluminum metallization of the contact pads against corrosion has been developed during the last three decades. In this method, the window in the dielectric protective overcoat (usually silicon nitride) is first opened to expose the metallization (usually aluminum or aluminum alloy) of the contact pad. Next, a thin layer of refractory metal which adheres well to both the aluminum and the overcoat is deposited. Then, a thin layer of noble metal is deposited with the intention to deposit solder (by evaporation or plating) over it. Descriptions of this technology have been published in the IBM J. Res. Develop., vol. 13, pp. 226-296, 1969: P. A. Totta et al., “SLT Device Metallurgy and its Monolithic Extension”; L. F. Miller, “Controlled Collapse Reflow Chip Joining”; L. S. Goldmann, “Geometric Optimization of Controlled Collapse Interconnections”; K. C. Norris et al., “Reliability of Controlled Collapse Interconnections”; S. Oktay, “Parametric Study of Temperature Profiles in Chips Joined by Controlled Collapse Techniques”; B. S. Berry et al., “Studies of the SLT Chip Terminal Metallurgy”.
These processes did not optimize the metallurgy for wire bonding (usually gold or copper) or for minimizing sensitivity to thermomechanical stress, especially in the protective overcoat. Further, the overall process is expensive, since at least ten process steps are involved.
In contrast to the metallurgical research, little effort has been made to protect the exposed edge sides of silicon integrated circuit chips. These edges sides have become increasingly more sensitive for microcracks unavoidably generated during the sawing process (length about 50 &mgr;m) and propagating from the sawing street sidewise into the silicon single crystal and the insulator layers. Moisture will follow the advancing cracks and start penetrating destructively the integrated circuit structures located next to the chip periphery. The reason for this recent upsurge in sensitivity is the ongoing cost-reducing trend of minimizing the silicon material reserved for the sawing lines; saw lines consume valuable silicon real estate and are therefore not useable for integrated circuit structures. As a matter of fact, the saw lines are shrunk so much in recent circuit designs and are thus positioned so close to the integrated circuit that sacrificial structures for arresting insulator cracks are now being proposed next to the sawing lines and fabricated in conjunction with the integrated circuit manufacturing processes (see, for instance, M. Ibnabdeljalil et al., U.S. patent application Ser. No. 60/073,939, filed Feb. 6, 1998). Even for the select few circuits types for which this approach has so far been proposed, the guaranteed reliability still has to be demonstrated.
A proposal to protect chip edges by a laser chemical vapor deposition technique is too expensive and too slow for mass production since this method processes the chips individually; see U.S. Pat. No. 5,451,550, issued on Sep. 19, 1995 (Wills et al., “Method of Laser CVD Seal a Die Edge”).
In U.S. Pat. No. 5,300,461, issued Apr. 5, 1994 (Ting, “Process for Fabricating Sealed Semiconductor Chip using Silicon Nitride Passivation Film”), a structure and process are described to first isolate individual chips fabricated in a semiconductor wafer by etch steps, which expose, in a sloped contour, portions of the silicon surface and the plurality of layers deposited upon the silicon surface. Second, a thin (less than 100 nm, UV light transparent) silicon nitride layer is deposited over the complete circuit surface, its exposed edge sides, and the exposed silicon surface. Third, non-corrosive conductive material is deposited for protection over the bonding pads. Fourth, a sawing step singulates the individual chips. While this proposed method is aiming at mass production, it requires extra photomask steps and does not use standard bonding processes. Because of its thinness, the sealant layer is at risk for thin spots and pin holes. The combination of etching and sawing consumes more valuable silicon than desirable. In summary, the method is expensive and not compatible with the mainstream of semiconductor technology. In addition, when integrated circuit chips are to be assembled into stacks, which is especially advantageous in memory products, then the assembly process becomes complicated when the chip edge sides are sloped or not in one plane
An urgent need has, therefore, arisen for a coherent approach to fabricating a hermetic semiconductor chip, consisting of a low-cost method of sealing the exposed edge sides after the singulation process, and a moisture-insensitive and low-stress protection of the contact pad metallization. The method should be flexible enough to be applied for different semiconductor product families and a wide spectrum of design and process variations, should provide assembly options for both wire bonding and solder connections, and should achieve improvements towards the goal of small outline and low profile packages—a persistent trend in today's semiconductor technology. Prefe
Archer Judith S.
Schroen Walter H.
Terrill Robert E.
Honeycutt Gary C.
Navarro Arthur I.
Telecky Fred
Texas Instruments Incorporated
Williams Alexander O.
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