Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2000-10-05
2004-11-09
Knight, Anthony (Department: 2121)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S015000, C703S019000, C703S023000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06816826
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention is related generally to simulation, which includes emulation, of the operation of a logic network, and more particularly, to ensuring asynchronous behavior is fully exhibited in such a simulation having rank-ordered logic operations.
2. Description of Related Art
As complexity of today's logic designs increases, more attention is being focused on validation techniques to insure quality, while allowing efficient time to market. This has motivated design reviews, and prompted verification of system level designs, where one or more components are brought together so that their interaction can be examined.
Simulation is the most widely used verification technique. A hardware accelerated version of simulation, ASIC-based processor array emulation has become mainstream. Herein, the term “simulator” is used to encompass both i) a conventional simulator, which uses a general purpose computer with a software model of a logic network under test, and produces a memory representation of inputs and outputs, and ii) an emulator, a special purpose device in which a design is represented, for example, in an array, rather than in a conventional CPU. Examples of emulators are disclosed in the following U.S. patents, which are hereby incorporated herein by reference: Lavi, “Hardware Logic Simulator,” U.S. Pat. No. 4,697,241; and Graves et al., “Apparatus and Method for Performing Behavioral Modeling in Hardware Emulation and Simulation Environments,” U.S. Pat. No. 5,946,472.
These simulation techniques are based on rank ordering a design net list, and evaluating the rank ordered net list on a cycle by cycle basis. To increase simulator performance, independent operations in the ranked order are separated and mapped to different processors for evaluation in parallel, which requires scheduling of results being passed from one operation to the next and also among the processors.
Once a model is built, rank ordered, and scheduled according to the present state of the art, problems arise regarding coverage of asynchronous events. That is, results of logic operations in a real network ripple through the network almost instantaneously. It is only at selected places in the network that the operations are timed, such as at a boundary between clock domains, for example, where operation results are latched periodically and information is shared across the boundary using handshakes, validity indications and the like. In contrast, a simulator evaluates simulated logic operations in parallel, to a certain extent, and also sequentially, on a regular frequency according to a simulator clock which has no particular relation to the clocks of the logic network. It is problematic that discrepancies may arise regarding functional behavior of an actual logic network, as compared to that of a simulated logic network, particularly with respect to results of logic operations which are performed at different clock rates and passed across boundaries.
SUMMARY OF THE INVENTION
These problems are addressed in a method, computer program product and apparatus for simulating operation of a logic network, according to which logic operations in a network model are partitioned into clock domains. Rank orderings are performed for operations in the respective domains. (A rank ordered set of operations is herein referred to as an “operation stack.”) Instances are identified of operations which are dependent on source operations from others of the domains. In a second set of orderings, pairs of the operations having common dependencies are separated, such as by inserting nop's, so that each pair has at least as many operations intervening therebetween as the total number of operations in the domains of the respective source operations. This separating enables input operations to take on new values between dependent evaluations, which is needed due to the operations are computed in all domains according to a “base clock” (i.e., either a system CPU clock or an emulator core clock),
It is an objective of separating selected operations, that after one value is computed for one instance of an operation depending on a source operation, a next value is computed for the source operation before computing the next instance of an operation depending on the source operation. That is, maximal asynchronous behavior is exhibited in the simulation, to achieve full coverage of asynchronous events.
In another aspect, the operations of all the domains are merged in an order that has a certain relation to the respective domain orderings, but omits any nop operations that were inserted previously. That is, in this first merged ordering the operation ranked first in the second ordering of the first domain is ranked first in this first merged ordering, unless it is not a nop, in which case it is omitted. The operation ranked first in the second ordering of the second domain, provided it is not a nop, is ranked next in this first merged ordering, and so on throughout all the operations of the domain orderings.
Then, in a second merged ordering, nop's are inserted in the first merged ordering, between pairs of the operations having a common dependency, so that the operations of such a pair are again separated to at least the extent as the previous separations.
It is an objective of the second merged ordering to reduce simulation time. That is, a reduced number of nop's are inserted, as compared to the individual domain orderings, because of advantageous use of overlap in intervening operations between pairs of operations having a common dependency.
It is an advantage of the present invention that any number of operation stacks are supported with any number of nop's, and the merging of the stacks results in an interleaving which tends to be fair for all domains, particularly when the domains have a similar number of operations. Also, although not necessarily yielding an absolute minimum of nop's, due to it's relative simplicity the result is obtained quickly.
These and other advantages of the invention will be further apparent from the following drawings and detailed description.
REFERENCES:
patent: 4697241 (1987-09-01), Lavi
patent: 5544067 (1996-08-01), Rostoker et al.
patent: 5649176 (1997-07-01), Selvidge et al.
patent: 5659716 (1997-08-01), Selvidge et al.
patent: 5946472 (1999-08-01), Graves et al.
Andersen Flemming
Baumgartner Jason Raymond
Klapproth Kenneth Douglas
Roberts Steven Leonard
England Anthony V. S.
Knight Anthony
McBurney Mark E.
Pham Thomas
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