Fully distributed slave ESD clamps formed under the bond pads

Details Fully distributed slave ESD clamps formed under the bond pads Fully distributed slave ESD clamps formed under the bond pads

2001-12-12

2003-12-23

Tibbits, Pia (Department: 2838)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

Reexamination Certificate

active

06667870

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit and, more particularly, to an ESD protection circuit that includes fully distributed slave ESD clamps that are formed under the bond pads.
2. Description of the Related Art
An electrostatic discharge (ESD) protection circuit is a circuit that protects the input/output (I/O) transistors of a semiconductor chip from an ESD event. An ESD event typically occurs when the chip is exposed to static electricity, such as when the pins or solder bumps of the chip are touched by an ungrounded person handling the chip, or when the chip slides across another surface on its pins or solder bumps.
For example, an ungrounded person handling a semiconductor chip can place a static electric charge as high as 2000V on the chip. This voltage is more than sufficient to destructively break down the gate oxide of the input/output transistors of the chip.
FIG. 1
shows a schematic diagram that illustrates a prior-art ESD protection circuit
100
. As shown in
FIG. 1
, circuit
100
, which provides ESD protection to a power pad
102
, a ground pad
104
, and a number of I/O pads
106
, includes an ESD plus ring
110
and an ESD minus ring
112
that extend around the periphery of a semiconductor chip
114
.
As further shown in
FIG. 1
, ESD protection circuit
100
includes a plurality of upper diodes D
1
that are connected to ESD plus ring
110
and the pads
102
,
104
, and
106
so that each pad is connected to ESD plus ring
110
via a diode D
1
. In addition, a plurality of lower diodes D
2
are connected to ESD minus ring
112
and the pads
102
,
104
, and
106
so that each pad is connected to ESD minus ring
112
via a diode D
2
. Circuit
100
also includes four corner clamps
116
that are connected to ESD plus ring
110
and ESD minus ring
112
.
In operation, when an ESD event occurs, a first pad A, for example, is zapped positively with respect to a second pad B. In this situation, a zap current IZAP flows from first pad A through the adjacent diode D
1
to ESD plus ring
110
, and then on to the corner clamps
116
. The corner clamps
116
are voltage controlled switches that each provide a low impedance pathway from ESD positive ring
110
to ESD negative ring
112
when an ESD event is present, and a high impedance pathway between rings
110
and
112
when an ESD event is not present.
When first pad A is zapped, the corner clamps
116
(which are shown open, not closed, in
FIG. 1
) close and the zap current IZAP flows through clamps
116
to ESD minus ring
112
. From ring
112
, the zap current IZAP flows through the diode D
2
adjacent to second pad B, and then onto second pad B.
FIG. 2
shows a schematic diagram that illustrates an example of corner clamp
116
. As shown in
FIG. 2
, clamp
116
includes a RC timing circuit
210
, an inverter
212
, and a switching transistor M
1
. Timing circuit
210
, in turn, includes a resistor R that is connected to an ESD plus ring, such as ESD plus ring
110
, and a capacitor C that is connected to resistor R and an ESD minus ring, such as ESD minus ring
112
.
Inverter
212
includes a PMOS transistor M
2
and a NMOS transistor M
3
. Transistor M
2
has a source connected to ESD plus ring
110
, a gate connected to resistor R and capacitor C, and a drain. Transistor M
3
has a source connected to ESD minus ring
112
, a gate connected to resistor R and capacitor C, and a drain connected to the drain of transistor M
2
. Further, switching transistor Ml has a source connected to ESD minus ring
112
, a gate connected to the drains of transistors M
2
and M
3
, and a drain connected to ESD plus ring
110
.
In operation, when an ESD event occurs and the zap current IZAP flows onto ESD plus ring
110
, the voltage on ESD plus ring
110
spikes up dramatically. The voltage on the gates of transistors M
2
and M
3
also spikes up but, due to the presence of RC timing circuit
110
, the gate voltage lags the voltage on ESD plus ring
110
.
As a result, the gate-to-source voltage of transistor M
2
falls below the threshold voltage of transistor M
2
, thereby turning on transistor M
2
for as long as the gate voltage lags the voltage on ring
110
. When transistor M
2
turns on, transistor M
2
pulls up the voltage on the gate of transistor M
1
, thereby turning on transistor M
1
. When transistor M
1
is turned on, clamp
200
provides a low impedance pathway from ESD plus ring
110
to ESD minus ring
112
.
The ESD protection circuitry used on a semiconductor chip is commonly considered to be part of the I/O cell structure of the chip. Typically, each I/O cell includes a pad, such as power pad
102
, ground pad
104
, or an I/O pad
106
, a section of an ESD plus ring, such as ring
110
, and a section of an ESD minus ring, such as ring
112
.
In addition, each I/O cell includes an upper diode, such as diode D
1
, that is connected between the pad and the ESD plus ring, and a lower diode, such as diode D
2
, that is connected between the pad and the ESD minus ring. Further, each I/O cell includes a section of a clean power ring, and a section of a clean ground ring. The clean power ring, which is supplied by a first power pad, and the clean ground ring, which is connected to a first ground pad, support the core circuitry of the semiconductor chip with substantially noise free power and ground connections.
Each I/O cell also includes a section of a dirty power ring, and a section of a dirty ground ring. The dirty power ring, which is supplied by a second power pad, and the dirty ground ring, which is connected to a second ground pad, support the noisy I/O circuits. In addition, each I/O cell typically includes I/O circuitry.
FIGS. 3A-3F
show a series of plan views that illustrate an example of the physical layout of a prior art I/O cell
300
. As shown in
FIG. 3A
, I/O cell
300
, which is formed in a layer of semiconductor material
302
, includes a diode
304
, such as diode D
1
of
FIG. 1
, that is formed in material
302
. In addition, I/O cell
300
includes a diode
306
, such as diode D
2
of
FIG. 1
, that is formed in material
302
.
Further, I/O cell
300
includes I/O circuitry
312
that is formed in semiconductor material
302
. I/O circuitry
312
can include, for example, MOS and/or bipolar transistors. Cell
300
also includes a number of contacts
314
that are formed through a first layer of dielectric material to make an electrical connection with diodes
304
and
306
and I/O circuitry
312
.
Referring to
FIG. 3B
, I/O cell
300
additionally includes a first pad P
1
and a number of first regions
316
that are formed from a first layer of metal. Pad P
1
and the first regions
316
, which include first regions
316
A and
316
B, are formed so that pad P
1
and the first regions
316
make electrical connections with contacts
314
. Cell
300
also includes a number of vias
320
that are formed through a second layer of dielectric material to make electrical connections with pad P
1
and the first regions
316
.
Referring to
FIG. 3C
, I/O cell
300
additionally includes a second pad P
2
and a number of second regions
322
that are formed from a second layer of metal. Pad P
2
and the second regions
322
, which include second regions
322
-A,
322
-B, and
322
-C, are formed so that pad P
2
and the second regions
322
make electrical connections with vias
320
.
Cell
300
also includes a trace
324
that is formed from the second layer of metal. Trace
324
is connected to pad P
2
, second region
322
-A, and second region
322
-B. Cell
300
also includes a number of vias
330
that are formed through a third layer of dielectric material to make electrical connections with pad P
2
and the second regions
322
.
Referring to
FIG. 3D
, I/O cell
300
further includes a third pad P
3
, a section of a first ESD plus ring
340
, and a section of a first ESD minus ring
342
. In addition, I/O cell
300
includes a section of clean power line
344
, and a section of a clean grou

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