Fully digital phase-locked loop

Details Fully digital phase-locked loop Fully digital phase-locked loop

1987-10-30

1990-11-06

Buczinski, Stephen C.

Cryptography

Key management

Having particular key generator

380 38, 375120, 328 63, 328155, 307511, 331 1A, 331 25, H04L 912

Patent

active

049691910

ABSTRACT:
A fully digital phase-locked loop comprises a sampler (1), an analog-to-digital converter (2), two quadrature demodulators (3 and 4) and their associated filters (5 and 6), and a decision logic (7) effecting the correction of the sampling phase around the value of the free-running frequency (f.sub.e) by the addition or subtraction of machine cycles of a signal processor (9).

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patent: 4680621 (1987-07-01), Baker et al.
patent: 4862104 (1989-08-01), Muratani et al.

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