Fully digital clock synthesizer

Details Fully digital clock synthesizer Fully digital clock synthesizer

1997-03-27

1999-07-06

Le, Dinh

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327105, 327113, 327114, 327261, 327269, 327294, 327299, H03B 1900, H03K 3017

Patent

active

059202114

ABSTRACT:
A fully digital clock multiplier capable of generating any N/M multiple of an input clock frequency with a precise duty cycle is provided. The input clock signal is divided by M to create a divided clock signal. The propagation of the input clock signal along a delay cell string during a half cycle of the divided clock signal is then measured. The measured propagation is then scaled by a factor N to select an appropriate delay cell string length within a ring oscillator for generating an output signal.

REFERENCES:
patent: 5216301 (1993-06-01), Gleeson, III et al.
patent: 5399995 (1995-03-01), Kardontchik et al.
patent: 5479125 (1995-12-01), Tran
patent: 5506878 (1996-04-01), Chiang
patent: 5530387 (1996-06-01), Kim

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