Fully differential self-biased signal receiver

Amplifiers – With semiconductor amplifying device – Including differential amplifier

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Details

330255, 330258, 330261, 330311, H03F 345

Patent

active

057035326

ABSTRACT:
A self-biased, fully differential, complementary receiver apparatus and method is presented. The receiver accepts differential inputs that can vary over the full rail-to-rail common mode voltage range. It produces double-ended complementary outputs swinging rail-to-rail useful in signal level conversion and comparator applications. The receiver includes a dual, fully complementary and mirror-symmetrical arrangement of a differential input stage, a biasing stage and an output stage. A self biasing voltage is generated with a balanced voltage divider coupled between the outputs of the biasing stages. This frees both biasing outputs for use as analogous but complementary receiver outputs while providing the receiver with all the advantages of self bias. For small signal differential inputs, the input and biasing stages operate in their linear region useful for amplifier applications. Whereas the circuit is most advantageously implemented using both p-type and n-type CMOS transistors, it can similarly be advantageously implemented with bipolar transistors. Alternate circuit configurations are described.

REFERENCES:
patent: 4937476 (1990-06-01), Bazes
patent: 4958133 (1990-09-01), Bazes
patent: 5006817 (1991-04-01), Babanezhad
patent: 5381112 (1995-01-01), Rybicki et al.
Cordaro, "Complementary FET Differential Amplifier", IBM Technical Disclosure Bulletin, vol. 16, No. 10, Mar. 1974 pp. 3227, 3228.
B. A. Chapell, et al., "Fast CMOS ECL Rceiver With Worst-Case Sensitivity," IEEE J. Solid State Circuits, vol. 23, No. 1, Feb. 1988.
M. Bazes, "Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers," IEEE of J. of Solid State Circuits, vol. 26, No. 2, Feb. 1991 .

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