Fully differential sampling circuit

Details Fully differential sampling circuit Fully differential sampling circuit

2002-02-26

2003-11-25

Jeanglaude, Jean Bruner (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S143000

Reexamination Certificate

active

06653967

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fully differential sampling circuit for single end input that performs fully differential sampling/holding on a single end input signal without an inverter amplifier and converts the signal to a fully differential sampling signal, and concerns an oversampling delta sigma A/D converter using the same.
Further, the present invention is characterized in that a linear term of voltage dependence of a capacitance is complementarily canceled regarding a capacitor formed on a semiconductor integrated circuit to reduce a sampling error appearing when an input signal is sampled, that is, to reduce second harmonic distortion which has been normally caused by a linear term of voltage dependence of capacitance of the capacitor.
2. Description of the Related Art
Recently, when an analog signal is handled on a semiconductor integrated circuit, the following methods are available: a method for handling a continuous-time analog signal as it is by an operational amplifier, a resistor, and a capacitor, and a method for sampling an analog signal at a predetermined sampling rate and processing the signal in a sampling time system.
In the latter method, an input differential pair is composed of a MOS transistor, and a MOS operational amplifier having no input leakage current has been developed. Thus, a so-called switched capacitor circuit has appeared, which is composed of an operational amplifier, a MOS switch, and a capacitor. The switched capacitor has been mainstream of analog signal processing until recently.
In addition to a switched capacitor filter, such technology of the switched capacitor circuit is applicable to a so-called a delta sigma modulator, which combines integrators on multiple stages and an A/D converter of a small number of bits and sends feedback of the result of A/D conversion to a first stage. The switched capacitor circuit is also applied to an oversampling delta sigma A/D converter which has been recently mainstream regarding an audio band.
Such a switched capacitor circuit firstly came as a single end type having only a signal system of a signal path. However, in response to the needs for a single chip combined with a digital circuit, which has become faster by the recent fine process, and a noise solution, a so-called fully differential switched capacitor circuit has become mainstream, in which signal paths are divided into two positive and negative systems and a difference therebetween is used as a signal level to cancel high-speed digital noise as in-phase noise.
Meanwhile, an ordinary analog signal is a single end signal centered at a certain input reference potential. Thus, in order to capture a single end signal to the fully differential switched capacitor circuit, the signal needs to be converted to a fully differential signal. Namely, when an input single end signal is used as a positive signal, it is necessary to produce a negative signal by inverting the positive signal.
The most typical method for producing a negative signal is to make inversion by an inverter amplifier and supply both of positive and negative signals to a fully differential switched capacitor circuit while maintaining a continuous-time system. As shown in
FIG. 6
, a single end input signal is used as a positive signal, the single end input signal is supplied to a positive signal input terminal
3
of a fully differential switched capacitor circuit
2
on a subsequent stage, an inverted signal is produced by an inverter amplifier
7
constituted by a single end operational amplifier
4
, an input resistor
5
, and a feedback resistor
6
, and the inverted signal is supplied to a negative signal input terminal
9
of the fully differential switched capacitor circuit
2
.
The fully switched capacitor circuit
2
samples/holds a fully differential input signal, which is a difference between positive signal input and negative signal input, according to a switched capacitor operating clock (CK). The fully switched capacitor circuit
2
performs a predetermined switched capacitor operation, outputs positive and negative signals respectively from a positive signal output terminal
11
and a negative signal output terminal
12
, and uses a difference between the output signals as a fully differential output signal.
As a specific example of the fully switched capacitor circuit,
FIG. 7
shows a fully differential switched capacitor integrator having the function of sampling/holding. The following will focus on the sampling/holding function and increased accuracy of the function.
Further, as shown in FIG.
8
(A), a capacitor
15
formed on a semiconductor substrate is generally constituted by two layers of polysilicon electrode plates
16
and
17
that contain N-type impurity such as phosphorus and a dielectric film
18
composed of an oxide film and the like between the electrode plates
16
and
17
. The capacitor
15
is formed on a semiconductor substrate
19
such as a silicon substrate. As symbols shown in a circuit diagram, capacitor symbols are used to separately represent first polysilicon serving as a lower layer and second polysilicon serving as an upper layer. The capacitor symbols represent the former layer as a curve and the latter layer as a straight line (FIG.
8
(B)).
The fully differential switched capacitor integrator of
FIG. 7
is constituted by a fully differential operational amplifier
20
, which has negative and positive input terminals
21
and
22
and positive and negative output terminals
23
and
24
, a first integral capacitor
25
which is disposed between the negative input terminal and the positive output terminal of the fully differential operational amplifier
20
and has a capacitance Ci, a second integral capacitor
26
which is disposed between the positive input terminal and the negative output terminal and has a capacitance Ci, a first sampling capacitor
27
which is disposed between the input terminal
3
and the negative input terminal (so-called summing node on the positive side)
21
of the fully differential operational amplifier
20
to perform the sampling/holding function of a positive signal and has a capacitance Cs, four switches
31
to
34
, a second sampling capacitor
28
which is disposed between the input terminal
9
and the positive input terminal (so-called summing node on the negative side)
22
of the fully differential operational amplifier to perform the sampling/holding function for a negative signal and has a capacitance Cs, and four switches
41
to
44
.
The following will discuss the operation of the integrator configured thus.
When an operating clock CK is in positive phase (&phgr;=H, &phgr;B=L), the switches
31
,
32
,
41
, and
42
are turned on, and the switches
33
,
34
,
43
, and
44
are turned off. Therefore, a lower layer electrode of the first sampling capacitor
27
is connected to the input terminal
3
via the switch
31
, and an upper layer electrode is connected to an operating common potential (analog ground) via the switch
32
. Further, a lower layer electrode of the second sampling capacitor
28
is connected to the input terminal
9
via the switch
41
, and an upper layer electrode is connected to the operating common potential via the switch
42
.
As a result, a positive signal from the input terminal
3
and a negative signal from the input terminal
9
are sampled at the first and second sampling capacitors
27
and
28
. When the input terminal
3
has a potential of VIN
+
and the input terminal
9
has a potential of VIN
−
, charges Q1 and Q2 of the following equations are respectively accumulated in lower layer electrodes
27
a
and
28
a
of the first and second sampling capacitors
27
and
28
.
Q
1=(
VIN
+
)·
Cs
Q
2=(
VIN
−
)·
Cs
Moreover, charges Q1′ and Q2′ of the following equations are respectively accumulated in upper layer electrodes
27
b
and
28
b
of the sampling capacitors
27
and
28
.
Q
1′=−
Q
1=−(
VI

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