Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2002-08-23
2004-06-22
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S172000
Reexamination Certificate
active
06753801
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an analog to digital converter, and to a reference voltage source for a pipeline analog to digital converter.
BACKGROUND OF THE INVENTION
Modern digital signal processing circuits are of central importance to recent advances in telecommunications, human/computer interface technology, image processing, and many other technologies. Analog to digital converters (ADC's) form an essential link in the signal processing pathway at the interface between the analog and digital domains. Advances in ADC technology have increased the speed, lowered the cost, and reduced the power requirements of analog to digital converters, and resulted in a proliferation of ADC applications.
Among existing ADC technologies are flash ADC, successive approximation ADC, Sigma-Delta ADC, and pipelined ADC. Flash ADC is performed by a highly parallel comparison of an input analog signal to each of a set of reference voltages. Flash ADC can provide very high speed and accuracy at the cost of high component count and high power consumption.
Successive approximation ADC uses one or a few comparators, operated iteratively, to yield high accuracy conversion with far fewer components than flash conversion. Successive approximation ADC, however, operates at much slower conversion rates than flash ADC.
Sigma-Delta converters provide high accuracy conversion by oversampling, but at conversion rates that are also significantly slower than flash conversion.
Pipeline ADC provides analog to digital conversion that, while slower than flash conversion, is faster than most other ADC architectures. Pipeline ADC's introduce a latency (delay) between analog signal input and digital signal output. Conversion throughputs of pipeline ADC's, however, approach those of flash converters. Unlike flash converters, for which component counts increase exponentially with converter resolution, the component counts of pipeline ADC converters increase linearly with resolution. Consequently, pipeline ADC converters are relatively compact, inexpensive, and power efficient. Accordingly, pipeline ADC's are widely used in portable signal processing apparatus.
Pipeline ADC's require stable, low noise, reference voltages for optimum operation. Preferably, these reference voltages are available at low cost in terms of chip real estate and power consumption.
FIG. 1
illustrates an exemplary pipeline ADC in block diagram form. The
FIG. 1
circuit is shown as a single ended ADC. In common practice, however, many pipeline ADC's are implemented as fully differential circuits. Nevertheless, single ended representation has been chosen for
FIG. 1
so as to reduce the complexity of the diagram, and enhance clarity of the disclosure. The exemplary converter
FIG. 1
includes a 10-bit pipeline ADC such as might be integrated on a single substrate with a CMOS Active Pixel Sensor (APS) array.
The pipelined ADC
100
includes a sample-and-hold stage
102
followed by 9 conversion stages
104
. Each conversion stage
104
includes a coarse ADC
106
for analog to digital conversion of a stage input signal received at a stage input
108
. The coarse ADC
106
produces a 1.5 bit digital output signal at an output
110
. A 1.5 bit output includes two output bits adapted to output only three possible states, rather than the four states available on a full 2 bit output. Each conversion stage
104
also includes a coarse digital to analog converter (DAC)
112
adapted to receive the 1.5 bit digital output signal of the coarse ADC
106
and produce a corresponding analog output voltage at an analog output
114
. The digital output of the ADC conversion stage is also coupled to a digital correction circuit
118
having a plurality of digital inputs
120
each coupled to a respective one of the 9 conversion stages
104
. Each conversion stage
104
further includes a subtracting node
122
with first
124
and second
126
analog inputs, and an analog output
128
. Also included in the ADC stage
104
is a high precision gain element (amplifier)
130
with a gain of two.
Operation of the above-described conversion stage
104
is as follows: an analog stage input signal is received at an input
107
of the coarse ADC
106
and at the first (positive) input
124
of the subtracting node
122
. The coarse ADC
106
produces a 1.5 bit output representing one of three possible values. This 1.5 bit output is applied to the digital input
113
of the coarse DAC
112
which, responsively, produces an analog output signal with a magnitude equal to one of three possible output signal values. As further discussed below, these three output signal values are +V
R
/4, 0, and −V
R
/4 where V
R
is a reference voltage of particular magnitude. The output signal of the coarse DAC is applied to the second (negative) input
126
of the subtracting node
122
. The subtracting node
122
produces an output equal to an arithmetic difference between the magnitude of the analog inputs at its first and second input terminals. This difference, referred to as a residual, is then applied to an input
131
of the high-precision gain stage
130
. The precision gain stage
130
produces an amplified residual output signal at its output
134
having a magnitude equal to two times the magnitude of the residual signal. This amplified residual signal is passed on to the input
108
of the next successive ADC stage
104
. Meanwhile, the digital output of the coarse ADC is received by the digital correction circuit
118
and logically combined with the digital outputs of the other 8 conversion stages
104
to produce a 10 bit digital output for the pipeline ADC at the output
140
of the digital correction circuit
118
.
FIG. 2
is a schematic diagram showing additional detail of the ADC conversion stage
104
described above with respect to FIG.
1
. Note that as in
FIG. 1
, the
FIG. 2
circuit is a simplified (single ended) representation of a circuit more commonly implemented as a fully differential stage. Accordingly, one sees an input terminal
108
, a coarse ADC stage
106
including first
202
and second
204
comparators each having a respective first input
206
coupled to the input terminal
108
and a respective second input
208
coupled to a respective source
210
,
212
of a respective reference voltage. The first
202
and second
204
comparators have respective first
214
and second
216
outputs coupled to respective first
218
and second
220
inputs of a digital latch circuit
224
.
The digital latch circuit
224
includes a control input
226
and a 2 bit wide digital output
228
. A coarse DAC
112
includes a multiplexer
240
with a 2-bit wide digital control input
242
, first
246
, second
248
, and third
250
analog inputs and an analog output
252
. The digital control input
242
of the DAC is coupled to the digital output
228
of the latch
224
. As is well known, the analog output
252
of the multiplexer is switchingly coupled to, and assumes the electrical potential of, one of the analog inputs
246
,
248
,
250
depending on a signal received at the digital input
242
.
The precision gain circuit
130
includes a high-gain differential amplifier
130
with a positive input
260
, a negative input
262
, and an output
264
. The positive input
260
of the amplifier
130
is coupled to a source of constant potential (e.g. ground potential
300
). The negative input
262
of the amplifier is coupled to a first plate
270
of a first capacitor
272
, and a second plate of a second capacitor
276
. The negative input
262
of the amplifier is also switchingly coupled to source of ground potential
300
by means of a switching device
280
. The first capacitor
272
has a third plate
282
switchingly alternately coupled to the output
264
of the amplifier
130
and to the input terminal
108
of the ADC converter stage
104
. The second capacitor
276
has a fourth plate
284
switchingly alternately coupled to the input terminal
108
of the ADC converter stage
104
, a
Dickstein , Shapiro, Morin & Oshinsky, LLP
Jean-Pierre Peguy
LandOfFree
Fully differential reference driver for pipeline analog to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fully differential reference driver for pipeline analog to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fully differential reference driver for pipeline analog to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3305917