Fully differential folding A/D converter architecture

Details Fully differential folding A/D converter architecture Fully differential folding A/D converter architecture

2001-01-17

2002-09-17

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

06452529

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to the field of electronic circuits, and more particularly to a system and method for performing analog to digital signal conversion using a folding A/D converter architecture.
BACKGROUND OF THE INVENTION
Important considerations in designing an analog-to-digital A/D converter are speed, component count, and resolution. Flash-type A/D converters provide, in many cases, the greatest speed. To convert an analog input voltage into an n-bit digital output code, a flash converter usually has 2
n
−1 input comparators that compare the input voltage with 2
n
−1 corresponding reference voltages supplied from a resistive voltage divider. The comparators thus trip at different levels based on their corresponding reference voltages and their outputs, which provide an indication of the input magnitude, are latched subsequently.
The principal disadvantage of the flash converter is a large component count due to the large number of input comparators. A large chip area is needed to implement the device in integrated circuit form. Numerous schemes have been proposed to cut the number of comparators (see, e.g., U.S. Pat. Nos. 4,270,118 and 4,386,339). These schemes normally accept a loss in conversion speed as a compromise.
A “folding” system is one of the more promising techniques for reducing component count. In a folding A/D converter, a set of input amplifiers respond to the input voltage and a corresponding set of reference voltages in such a way as to generate one or more pairs of complementary waveforms that have a repetitive rounded triangular shape as a function of the input voltage. A group of fine comparators convert these sawtooth waveforms into a string of bits which are encoded into the least significant bits of the output code. The most significant bits ere supplied from a group of coarse comparators which operate on-the input voltage along a separate channel from the folding array.
The chip area for a folding A/D converter is reduced dramatically because it utilizes considerably fewer circuit components than an otherwise equivalent flash converter. By converting the analog input into a piecewise-linear periodic function of the input signal, the output of the A/D converter exhibits a dramatically reduced dynamic range than its corresponding input signal. Consequently, the AND converter is desirable over conventional converters in certain circuit applications because the folded waveform can be digitized utilizing substantially fewer-latches, thereby reducing die area and power consumption.
An exemplary conventional 6-bit folding A/D converter circuit exhibiting a 2-to-1 type folding function is illustrated in prior art
FIG. 1
, and designated at reference numeral
100
. The A/D conversion is made by comparing a differential analog input signal
102
a
,
102
b
with 64 uniformly spaced differential reference voltage levels
104
(e.g., V64+, V64−, V63+, V63−, etc.). The differential reference voltage levels
104
may be derived from two voltage divider circuits which include 63 series-connected resistors and is sometimes referred to as a resistor ladder.
As illustrated in prior art
FIG. 1
, the 2-to-1 folding scheme includes 32 folders
106
involving 64 comparator or pre-amplifier circuits
108
and
32
dummy comparator or pre-amplifier circuits
110
. To form a folder
106
, for example, the differential output nodes of pre-amplifier P
64
and P
32
, along with dummy pre-amplifier D
32
, are connected together and coupled to a latch
112
in the manner illustrated. The input of each dummy pre-amplifier
110
is configured such that one side of the input differential pair (not shown) is conducting all the current and the other side is cut off.
When the analog input signal
102
a
,
102
b
is at a level close to the differential reference voltage level associated with pre-amplifier P
64
(V64+, V64−), P
64
is functional (causing its output to trip) while the current contributions from P
32
and D
32
to their output nodes are balanced. Similarly, when the analog input signal
102
a
,
102
b
is at a level which is close to the differential reference voltage level associated with the pre-amplifier P
32
, P
32
is functional while the current contributions from P
64
and D
32
are balanced. Therefore each folder
106
provides indications which correspond to two different “zero-crossing” points when the analog input signal
102
a
,
102
b
varies across its full range. Consequently, only half the number of latches
112
and corresponding digital processing circuitry (not shown) are needed, compared to a conventional full flash A/D architecture.
Although the prior art folding A/D converter
100
of
FIG. 1
exhibits advantages over conventional flash AND architectures, the circuit layout of the converter
100
has some problems, particularly in high speed converter applications, for example, of about 500 MS/s or more. When the pre-amplifier circuits
108
are laid out as shown in
FIG. 1
, the electrical connections between the resistor ladders
104
and the appropriate pre-amplifiers are relatively short and simple, however, the folder output node connections are not. In particular, the output connection distance associated with pre-amplifiers and a latch in a single folder
106
(e.g., P
64
, P
32
and D
32
) is substantial, as illustrated. The relatively large and complex folder output electrical layout connections result in an undesirably large parasitic capacitance at each folder output node. The large parasitic capacitance operates to reduce the speed of the converter and/or makes the converter consume a larger amount of power to achieve a specific desired speed.
Once conventional solution to the above problem with an undesirably large parasitic capacitance is to lay out the pre-amplifiers associated with a given folder proximate or geometrically close to one another. With such a configuration, the pre-amplifiers associated with a given folder are proximate or local to one another (e.g., P
64
, P
32
and D
32
), and the output electrical connection distance for a particular folder is substantially reduced. Unfortunately, such a pre-amplifier layout configuration creates a problem with respect to the connection of the pre-amplifiers
108
to the differential reference voltage levels of the resistor ladder
104
. Because the numerical order of the pre-amplifiers has been broken (as can be deduced from FIG.
1
), but the differential reference voltage levels still follow a numerical order, as illustrated in
FIG. 1
, a tremendous amount of complex wiring and wiring-related issues (e.g., cross-over connections, line resistance) arise at the pre-amplifier inputs. Such wiring complexity issues are further exacerbated for N-to-1 folding architectures when N is greater than 2.
There is a need in the art for high speed folding A/D converters which overcome the limitations associated with the prior art.
SUMMARY OF THE INVENTION
The present invention relates to a folding A/D system architecture and method for reducing folder output parasitic capacitance while concurrently exhibiting a differential reference voltage circuit which is configured spatially to simplify the connections therefrom to the folder inputs, thus overcoming the disadvantages associated with the prior art.
The present invention comprises a differential folding A/D converter architecture. The architecture comprises a folder portion containing a plurality of folders in which multiple pre-amplifier circuits associated with a given folder are laid out or otherwise configured proximate one another to thereby reduce the length and complexity of the output connections associated therewith and thus reduce parasitic capacitance. In addition, the architecture comprises a differential reference voltage generation circuit, for example, a series-connected resistor ladder, operable to provide a plurality of differential reference voltages to the folder portion. Unlike the prior art, the differential reference voltage gener

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